²ÝÁñÉçÇø

Ever-increasing expectations for mobile device performance have been driving the need for versatile mobile memory solutions. JEDEC has recently announced the publication of JESD209-5A which is equipped to match the latest bandwidth, power, performance, and reliability trends. The JESD209-5A standard offers several feature enhancements in addition to the existing LPDDR5 standard, including support for Partial Array Refresh Control (PARC), Refresh Management, Enhanced Write Clock (WCK) Always On Mode, Optimized Refresh, etc. This blog will briefly discuss the new features introduced in the updated LPDDR5 standard which has helped to significantly reduce power consumption and improved in data integrity.

Optimized Refresh

The self-refresh operation allows deactivation of the clock to reduce the power consumption of the device and it automatically executes the internal refresh operation by using the internal refresh events. The use of the ¡°Self Refresh¡± mode introduces the possibility that an internally timed refresh event can be missed when ¡®Self Refresh Exit¡¯ is registered, requiring an additional Refresh command before entry into a subsequent Self Refresh mode. This additional refresh requirement can be managed efficiently if both, memory controller and SDRAM can track their internal refresh timer values for tREFI window outside of the self-refresh time period.

Enhanced Write Clock (WCK) Always On Mode

The easy option is to synchronize the signals once and then keep WCK running constantly to maintain synchronization (this is known as ¡°free running mode¡±). While this option requires little ingenuity, it does come at the expense of system power. Given most LPDDR5 devices will be used in the mobile market, the desire to save power is pertinent, which means the system must turn off WCK whenever it isn¡¯t absolutely required. Turning off WCK requires a resynchronization of WCK to CK before any data transfer can occur. In order to manage this efficiently, the LPDDR5 memory controller schedules commands so that synchronization operation does not add unnecessary latency. In Enhanced WCK Always On Mode, the controller can issue a special command known as CAS-WCK_SUSPEND command which allows SDRAM to reduce some of the internal WCK clock net power consumption. WCK SUSPEND mode requires WCK continue toggling and exits automatically by following Read or Write or Mask Write command without issuing any additional explicit command.

Partial Array Refresh Control (PARC)

LPDDR5 SDRAM allows banks to be configured as segments. These segments can be individually masked, skipping the requirement to refresh segments where Partial Array Self Refresh (PASR) Segment Mask is defined when All bank or Per bank Refresh command is received to reduce power consumption.

Write X Steering Control

Write X is a power-saving feature that allows the SDRAM to write a specific bit pattern (such as all-zero or all-one pattern) to contiguous memory locations without requiring WCK toggling and data input to SDRAM¡¯s DQ pins. Programming the Write X Steering bits controls the pattern (either 1¡¯s or 0¡¯s) at a byte level control via the command.

Non-Target SDRAM ODT

LPDDR5 SDRAM supports the Non-Target DRAM ODT function for DQ, DMI and RDQS pins to improve signal integrity in a 2-rank configuration by impedance matching of the lines. Non-Target ODT allows the SDRAM to work at a higher data rate without signal distortion.

DVFSQ Mode

LPDDR5 SDRAM supports different VDDQ levels for high speed operations. This allows the VDDQ to be ramped up quickly during high speed operations including Read/Write transactions.

Conclusion

From the wide array of features introduced in LPDDR5 we can see that this VIP is much more powerful and equipped to be used in applications like medical imaging, automotive, AI, ML, etc. ²ÝÁñÉçÇø has been engaged with the early adopters of LPDDR5 VIP since 2016. For more information on ²ÝÁñÉçÇø memory VIP, please visit