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One question which came up recently in several customer discussions is one which boils down to “What is DMA and what good is it to me?” To answer that, we need to look at a bit of context. DMA stands for “Direct Memory Access” and originally a “DMA controller” referred to a separate chip which could be used by a CPU to move blocks of data around in memory without using a lot of CPU cycles. In the context of PCI Express controllers, we no longer have (or want!) a separate chip, but plenty of designers still find uses for a separate block of logic they can use to move data without burdening their CPU(s). Sometimes this is a part of the application-specific logic in a chip, and sometimes it’s a more generic piece.
DMA Defined
In its most basic form a DMA controller is given a source address, a destination address, and a count and told to go. Sometimes this collection of information is called a “Scatter/Gather Element” or “SGE” in engineering acronymics. Typically the DMA controller will generate an interrupt of some sort once the work is completed and wait to be programmed with more work. Of course modern DMA controllers have more complex control structures. Typically they can process whole lists of SGEs – called “Scatter/Gather Lists” (SGLs) or just “Linked Lists” – before needing additional programming. Not coincidentally, modern operating systems generate SGLs internally when they’re constructing I/O requests to devices like storage and networking controllers. (Since virtual memory systems tend to scatter a program’s data structures across a range of physical addresses, the operating system would really like the controller hardware to handle all that mess rather than asking the host CPU to split up and move around big chunks of program data.)
Because there are often multiple pieces of application logic wanting to move data, it’s fairly common for DMA controllers to provide several “channels” or independent sets of controls and logic for moving data. This way the various applications don’t have to arbitrate among themselves for access to a single set of DMA control registers, the designer can give them each their own set. (Yes, this is just like those dual-headed media players they sell for the back seat of your car. “Stop bothering your sister and watch your own movie!”) While you probably want to make sure that brother and sister in the back seat each get equal access to their media players, life may not be so simple in an SoC. In many applications there are inherent priorities among the application tasks you’re designing and here you might wish to make sure one doesn’t hog the PCIe bus! At least in the 草榴社区 implementation of multi-channel DMA, we can do that. Each DMA channel in our system can be programmed with a “weight” which is used when multiple agents are trying to use the bus at the same time. The weight ensures that the programmer/designer controls the bandwidth division among agents – not the “piggishness” of the agents involved.
Hopefully by now you’re starting to think of your own answer to “What good is DMA to me?” but in case you need a little push, consider a few things:
- Is your application going to be processing work which comes in Scatter/Gather form from the operating system already?
- Are you depending on a CPU of some sort to move data around your system?
- Do you want to divide up the available system bandwidth among multiple agents?
If you answer “yes” to any of the above, you should consider using a DMA controller in your SoC design.
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