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• ²ÝÁñÉçÇø demonstrated 2 setups that we¡¯re interoperable with multiple vendor devices
• Setups were tested with AI accelerators, memory expanders, retimers, and host devices
• ²ÝÁñÉçÇø executed CXL Compliance Verification (CV) tests for CXL1.1 and CXL2.0

The CXL Consortium Compliance Test Event 002 (CTE 002) took place October 2-6, 2023 in Portland, Oregon, US. The event enabled consortium members to test their solution¡¯s interoperability with other consortium members and vendors. Members were allowed to test compliance specified testcases and check their product¡¯s Interoperability in the field. 

²ÝÁñÉçÇø protocol verification experts demonstrated 2 setups covering host and device configurations by using ²ÝÁñÉçÇø Virtual System Adaptor (VSA), Speed Adaptors (SA) and transactor over ZeBu? EP1, the industry¡¯s fastest emulation platform. See figures below for the Host and Device setups presented.

Testing CXL Vendor Devices with ²ÝÁñÉçÇø CXL Host Solution

Testing Intel/AMD Server with CXL Controllers with ²ÝÁñÉçÇø CXL Device Solution 

²ÝÁñÉçÇø demonstrated protocol solution interoperability and completeness for post-silicon industry devices. Teams ran all of the CXL CV software testcases for CXL 1.1 and CXL 2.0 specification devices.  

At the end of the event, we were able to prove the ²ÝÁñÉçÇø CXL host protocol solution for 20+ Type1, Type2 and Type 3 CXL endpoint devices coming from 10 different vendors. The ²ÝÁñÉçÇø CXL device configuration solution was able to pass CXL CV testcases with available Intel and AMD enabled servers.

²ÝÁñÉçÇø provides CXL 3.0/2.0/1.1 protocol solutions for ²ÝÁñÉçÇø VCS? , ZeBu, and HAPS? solutions. We work closely with the CXL consortium on the new specification adoption and providing solutions to our early partners. 

²ÝÁñÉçÇø provides ZeBu server transactors, memory models, and speed adapters supporting a broad set of portfolios with over 100 protocols which help customers quickly develop complete system-level test environment for SoC designs to be verified in pre-silicon. Running system-level payload on SoCs requires a fast hardware-based pre-silicon solution. ²ÝÁñÉçÇø transactors, memory models, hybrid and virtual solutions based on ²ÝÁñÉçÇø IP enable various verification and validation use-cases on the industry¡¯s fastest verification hardware systems, ²ÝÁñÉçÇø ZeBu? and ²ÝÁñÉçÇø HAPS?.