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Planning which metal shape goes on which color (mask) is key when designing in a FinFET process, especially when propagating connections through the layout hierarchy. In addition, highly matched signals such as complementary clocks must be assigned to the same color, as routes on different masks have different resistances. So how do we ensure we are keeping things in order with respect to the matching of resistance and capacitance?

Custom Compiler¡¯s In-Design assistants include a ¡®built in¡¯ engine that computes resistance of a net from a single source to a single destination or multiple destinations. It is an interactive tool that can be run often during the layout process, has a simple use model and a fast response time. To report the resistance of a net, the layout engineer simply selects the net of interest from either the layout, the design navigator or the schematic. The next step is to invoke the resistance report command which pops up the electrical report menu. The report type is set to resistance and the source and destination points are entered.  The report is run and the results are populated into the Electrical Reporter pane.

Total resistance and total length for each source and destination point is shown in the top portion of the pane. Selecting one of the source and destination points reveals more detailed information on the contribution that each individual wire makes to the total resistance and length.  Selecting an individual wire in the lower portion of the pane highlights the wire in the physical layout. Armed with this wealth of information the layout engineer can quickly make changes such that the design meets the electrical specifications. Figure (1) shows the results of running the resistance report.