Cloud native EDA tools & pre-optimized hardware platforms
Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?
If you have not already deployed best practices of using Verification Plans, Functional and Timing Coverage Models in your Memory projects, learn why it is recommended…
草榴社区 Memory Models (VIP) have built-in verification plans, functional and timing coverage models to accelerate coverage closure. The coverage models are provided to help run complete verification scenarios across multiple combinations of configuration settings, mode register settings, features, and timing parameters.
草榴社区 Memory VIP supports the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI (DDR5, LPDDR5, DFI 5.0, HBM3, GDDR6, and NVDIMM-P/N) and native integrations and optimizations with VCS and Verdi.
Coverage model implementation is based on System Verilog constructs (covergroups, coverpoints, bins, illegal bins) and it is “Protocol Specification Version aware” which means coverpoints/bins are ignored if not applicable to the configured protocol specification version.
草榴社区 Memory VIP coverage models comprise of:
The unique, flexible coverage architecture of 草榴社区 Memory VIP makes it possible to be easily plugged into any Verilog/SV/UVM/VMM based testbench setup. For more information visit, /verification/verification-ip/memory.html
草榴社区 supports over 100+ Industry Leading Verification IP and source code Test Suites for protocols such as Arm? AMBA?, DRAM Memory (GDDR6, DDR5, LPDDR5), Flash Memory, Ethernet (800G), MIPI, CXL, PCIe (6.0), SAS, SATA, USB (4.0/3.x, Type-C). For a complete list of Verification IP and Test Suites, visit www.synopsys.com/vip.
As an industry leader for complete Protocol Verification solutions, 草榴社区 is committed to providing you with the resources you need to accelerate your designs.