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²ÝÁñÉçÇø offers a broad set of verification solutions for next generation Arm? AMBA? protocols, including AMBA CHI Issue B, and verification automation solutions including Auto SoC Testbench Generation and AutoPerformance for AMBA protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of ²ÝÁñÉçÇø¡¯ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of source code test suites and VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications.

 the availability of AMBA ACE5 and AXI5 as a part of the AMBA 5 family of protocols, enhancing the standard architecture for next-generation interconnect designs. ²ÝÁñÉçÇø has collaborated with Arm on the creation of this specification and to deliver ²ÝÁñÉçÇø VIP for ACE5 and AXI5 with increased performance for faster verification closure. ²ÝÁñÉçÇø¡¯ VIP for ACE5 and AXI5 is industry¡¯s first source code test suite and VIP for the latest AMBA specifications.

AMBA ACE and AXI are used pervasively across a wide range of SoC designs, and ACE5 and AXI5 provide significant performance improvements over previous generation AMBA interconnect protocols. Both of the latest specifications add new features for atomic operations to improve the performance, and data check and poisoning to identify data corruption. These also add new low power wakeup signals to provide a single, glitch-free indication showing that activity on the interface is required. In addition, ACE5 has added support for cache stashing to improve data locality, new de-allocating and cache maintenance transactions, as well as DVM message support for Armv7, Armv8 and Armv8.1 Cortex-A processors.

²ÝÁñÉçÇø VIP and test suite makes it easy for designers to adopt the latest protocol specifications and achieve multifold productivity gains. Below is a summary of ²ÝÁñÉçÇø¡¯ VIP and test suites advanced verification features:

• Comprehensive UVM source code test suites
• Configurable interconnect model
• System env
• System monitor, which performs system-level checks for protocol, data integrity and cache coherency
• Reference verification platform
• Performance metrics for latency and throughput analysis
• Native integration with Verdi? Protocol Analyzer and Performance Analyzer
• Built-in coverage and verification plans for accelerated verification closure

Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. ²ÝÁñÉçÇø test suites help eliminate the task of writing tests for today¡¯s complex protocols. The test suite is a complete self-contained, configurable environment and provided as System Verilog UVM source code to simplify integration, enable extension, customization, and maximize reuse across projects. Users can easily customize or extend the UVM source code provided for verification environment and tests to include DUT or application specific tests. Test suites are updated, expanded and new tests are added with each release of new protocol specifications. A built-in verification plan is provided with spec linking and coverage.

²ÝÁñÉçÇø collaborates with standards organizations, SoC leaders and market makers, and proactively contributes to the development of next-generation specifications. For example, in June, 2017, concurrent with Arm¡¯s announcement of AMBA 5 CHI (Coherent Hub Interface) Issue B, .

Later in Oct, 2017, ²ÝÁñÉçÇø announced Verification Automation ²ÝÁñÉçÇø for Arm AMBA Coherent Interconnects. ²ÝÁñÉçÇø¡¯ Auto SoC Testbench generation solution enables easy and quick integration and configuration of hundreds of coherent and non-coherent AMBA ports and corresponding VIP instances. The AutoPerformance solution enables users to define traffic profiles for measurement of performance metrics like throughput and latency, and drive stimulus with ²ÝÁñÉçÇø¡¯ VIP for AMBA (CHI/ACE/AXI).

Also read our blogs on AHB5 ¨C Arm AMBA 5 AHB5: Accelerating the Embedded and IoT World, and ACE ¨C Jumping the Barrier of Verifying Arm AMBA ACE Protocol Barrier Transactions. For more information on the architecture and scope of the SystemVerilog source-code test suites watch our video blog SystemVerilog Protocol Compliance: Why Source-code Test Suites? To learn more about ²ÝÁñÉçÇø VIP and test suites for AMBA protocols, please visit .