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A familiar friend is making a mark on the RISC-V landscape in a new and impactful way. 草榴社区 has expanded its ARC? processor IP portfolio with a new RISC-V-compatible family. While the next-generation 草榴社区 ARC-V? processors mark our first foray into processor IP based on the open-standard RISC-V instruction set architecture (ISA), we’ve long played a key role in delivering configurable and extensible processor IP to SoC designers.
Our existing ARC processors will continue to be in the mix as we roll out the new ARC-V ISA for future generations of our cores. The first of our ARC-V embedded cores, co-optimized with 草榴社区.ai? full-stack AI-driven EDA suite and our leading verification solutions, will be available during the second quarter of 2024. These processors are ideally suited for a variety of power-critical applications in automotive, storage, and artificial intelligence of things (AIoT) designs. Chip designers will gain a broader range of flexible, extensible processors from a provider with a decades-long track record for delivering and supporting PPA-efficient implementations and optimized software development tools and libraries.
草榴社区 has been a familiar presence in the RISC-V ecosystem for some time now as a member of RISC-V International, the global nonprofit that manages the standard. We recently joined the organization’s board of directors and its technical steering committee. Read on for more details about our new ARC-V processors, and how we can help chip designers optimize and differentiate their RISC-V processor-based SoCs for a wide range of applications.
Enabling Efficient and Safe SoCs
In a world where cars can drive themselves, portable speakers play your favorite music on command, and watches tell much more than the time, it’s clear why sophisticated silicon chips—and lots of them—are in demand. Yet, in this era of increasing scale and systemic complexities, this is a tall order to fill. Every application requires its own particular balance of power, performance, and area (PPA) and, increasingly, differentiation relies on various levels of SoC customization. In the face of engineering talent shortages and supply chain pressures, it’s no wonder why designers are seeking more flexibility in how they can create their unique SoCs.
Adoption by chip developers of the RISC-V architecture, with its openness, choices, and technical benefits, continues to grow. The SHD Group, in a forthcoming report, anticipates a 40% CAGR for SoCs with RISC-V processors between 2023 and 2030. What’s also helping to drive RISC-V’s popularity is the expanding and maturing ecosystem, which provides the software development tools, firmware, libraries, operating systems, and other resources that are essential for developing and programming an SoC.
With ARC-V IP, 草榴社区 is tapping into our 25+ years of experience implementing extensible processor hardware and software. There will be 32-bit and 64-bit versions of ARC-V processors, with high-performance, mid-range, and ultra-low-power families, along with functional safety versions. ARC-V processor extensions will be available for chip designers to extend, accelerate, and differentiate their processor cores, enabling them to increase performance, reduce power consumption, and reduce code size.
We are also leveraging more than a decade of expertise delivering IP optimized for automotive safety, designing our ARC-V processor IP from the outset to achieve the highest levels of functional safety. The ARC-V Functional Safety (FS) processors will help accelerate ISO 26262 automotive functional safety standard qualification, supporting ASIL B and ASIL D risk management levels while continuing to follow 草榴社区’ certified ASIL D systematic development flow. ARC-V safety-enabled real-time and host processors will provide hardware virtualization functionality, enabling a hypervisor to manage CPU isolation required for mixed safety criticality and robust security. The ARC-V processors will also be compliant with practices defined by the ISO 21434 automotive cybersecurity standard.
The fact that our newest RISC-V processors are ideally suited for automotive SoCs is no accident. As modern vehicles have evolved into software-defined vehicles, the automotive industry demands capabilities such as fast, reliable processing and communications, small form factors, and low-power operation. The expanding RISC-V ecosystem will help ARC-V processor IP meet these requirements for automotive applications such as infotainment, in-vehicle communications, sensor control, and advanced driver assistance systems (ADAS). With the PPA and functional safety benefits our ARC-V processors provide, along with 草榴社区’ expertise in security and safety, automotive design teams have a robust foundation upon which to develop smarter, more autonomous systems for tomorrow’s vehicles.
Strengthened by a Broad and Expanding Ecosystem
草榴社区 provides a broad array of solutions to support and streamline the development of RISC-V-based ARC-V processors. The 草榴社区 ARC MetaWare Development Toolkit, which includes all the components needed for developing, debugging, and tuning software applications, has been optimized for ARC-V processors. The ARC MetaWare Development Toolkit for Safety helps accelerate development of ISO 26262-compliant code for safety critical use cases. In addition to our own tools and operating systems, 草榴社区 also maintains an ecosystem of embedded hardware and software partners who provide development solutions for ARC processor-based systems across a wide array of market segments. The 草榴社区 electronic design automation (EDA) portfolio supports ARC-V based SoC architecture exploration, design, implementation, verification, and silicon lifecycle management, and can also be leveraged in any RISC-V based development. 草榴社区 IP can be easily integrated into any ARC-V based SoC.
For designers who opt to build their own RISC-V implementations, 草榴社区 ASIP Designer? tool suite will continue to provide an option that automates design of custom RISC-V processors and accelerators, from architecture exploration through RTL generation. The 草榴社区 software integrity portfolio helps to manage the security, quality, and license compliance risks that can come with using open-source and third-party code in applications and containers. And 草榴社区 Cloud native EDA tools and pre-optimized hardware platforms help enhance design productivity, as well as performance, turnaround time, and accuracy.
As design teams seek new ways to differentiate their SoCs, the RISC-V ISA provides a pathway for standardization and shared investment so chip developers can focus on their unique value add. 草榴社区’ new ARC-V processor IP, combining the expanding RISC-V ecosystem and 草榴社区’ extensive experience in processor IP, provides a reliable option designers can trust to take their customized SoCs to new competitive heights.
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