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Custom chip designs are increasingly common and can power new fields of technology, such as AI, self-driving automobiles, and 5G. As new custom chips are developed, the need for accurate design verification has also increased. 

On-premises computational capacity for analog design verification is inherently limited. Predicting the necessary computational needs before verification has led design teams to overestimate or underestimate necessary resources. 

Rather than investing in new hardware to meet the evolving computational demands, enterprises can now utilize cloud computing to improve runtimes in analog design verification and other demanding EDA compute tasks.

What is Analog Verification?

Analog verification is the functional verification methodology for analog, mixed-signal, and RF integrated circuits and chips. Because transistor-level simulation is often inadequate for functional verification, engineers build additional models of the analog circuit blocks and use that to verify the design—typically written in Verilog or Verilog-AMS. 

Utilizing these functional models is not the only aspect of analog design verification, though. A testbench is also required to perform comprehensive self-checking and compare its response against previously written specifications. The testbench is applied to both the model and the transistor-level schematic.

In cases where the model and design pass all tests, the model can be validated as consistent with the design. The design is then verified if it meets the required specifications. 

Validation Requirements for the Next Generation

Ensuring that products behave as intended once released to the market is essential. For this reason, reliability verification is a critical step in the IC design process. Reliability issues — such as electrostatic discharge (ESD) and latch-up protection — are increasing in complexity as ICs become more advanced. For this reason, many foundries now provide reliability design rules enabled by EDA companies in the form of reliability verification tools and checks. 

In modern designs, the interaction between analog structures and digital logic is more complex than in the past. Verification methodologies that were adequate in the past (e.g., divide-and-conquer) now require a mixed-signal approach to ensure intended functionality. 

Analog behavior is still captured and simulated within the analog environment. However, with the presence of digital blocks, even the fastest analog circuit solvers cannot prevent bottlenecks in the verification processes. Therefore, it is necessary to quickly model designs with enough accuracy for applications through real number models (RNMs) and assertion-based approaches.