Cloud native EDA tools & pre-optimized hardware platforms
草榴社区 Synplify? software offers FPGA designers an automated means to build into their design functional safety, high uptimes, and highly reliable design operation. These designs become resistant to radiation-induced errors and other single bit flips that might otherwise result in incorrect operation or, even, system lock-up. As FPGA device geometries shrink, this solution is becoming a “must have” for systems deployed in industrial, medical, automotive, communications, military and aerospace applications.
Industry standards including DO-254, IEC 61508 and ISO 26262 define functional safety and error mitigation strategies for the creation and validation of high reliability systems. The Synplify tool automates industry methods for mitigating soft errors such as single-event upsets (SEUs) that are increasingly present in the latest FPGA process geometries. Synplify provides two essential elements to automate SEU immunity and create safe designs that operate with high reliability in radiation-rich environments.
Using Synplify Tool, FPGA designers have multiple options for implementing error detection and mitigation circuitry, such as:
Synplify tool can automatically create error monitors and error flags, accessible either externally or internally within the design. Coupled with the ability to tap any node via the FPGA I/O to facilitate probing or fault injection for verification, Synplify tool helps to accelerate implementation and test of high reliability designs.