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The industry trend in AI and HPC is rapidly advancing towards chiplet-based designs for achieving the highest levels of performance, as the traditional monolithic system-on-chip (SoC) designs are struggling to scale. Heterogeneous integration is driving innovation in the semiconductor industry. However it also increases the complexity of chip design, leading to more advanced testing methodologies and improvements in automatic test equipment (ATE) to maintain signal integrity, accuracy, and performance.

As the complexity of semiconductors increases, structural testing of devices becomes more challenging which requires high-bandwidth test data interfaces for at-speed testing, to confirm truly known-good devices (KGDs) and to achieve high test coverage and a low DPPM number in a reasonable timeframe. Ensuring the highest test coverage for individual chiplets is crucial, before integrating them into complex 2.5D or 3D packages, to prevent yield fallout once they are combined with other chiplets in a complete package.  

The number of patterns required to test these complex devices has increased significantly, coupled with the fact that there are a limited number of general-purpose IO (GPIO) pins to perform the tests. GPIO speed restricts test data throughput, reducing overall coverage to test today¡¯s designs efficiently and though the conventional High-speed I/O protocol (PCIe/USB) satisfies the bandwidth requirements, it requires expensive hardware setup.

Increasing testing costs with complex heterogeneous chips

In HPC and AI computing chips, as functionality becomes increasingly complex, the number of validation steps also grows significantly. However, in scenarios where the number of IO pins is limited, the bottleneck often lies in validation time, which extends the product development cycle and significantly increases the test costs. 

The limited availability of high-band width test access ports, especially in multi-die design, highlights the need for an IO which can operate at much higher speeds than GPIO but adds no additional hardware components or complex protocol support on initialization/calibration sequence, while maintaining signal integrity for the latest manufacturing processes. 

²ÝÁñÉçÇø High-Speed Test GPIOs (HSGPIO) are optimally designed to meet these high-speed test requirements. The versatile offering from ²ÝÁñÉçÇø ensures the single IOs can be multiplexed based on their usage as ¡®test ports¡¯ during manufacturability, performing ¡®high-speed clock observation¡¯ during debug and configurable to ¡®GPIO¡¯ during production, making them unique in the industry in supporting comprehensive test needs.

Enhancing IP Performance & Optimizing Power with Multiple Modes

In moving towards chiplet design, many of the regular high-speed interfaces are no longer available on some of the individual chiplets. The die-to-die interfaces like HBM and UCIe handle the communication between the chiplets and occupy most of the ports available for connection, which limits the number of interfaces suitable for external test access. As package pins are precious, ²ÝÁñÉçÇø High-Speed Test IO enables re-use of the same high speed test pins as low power GPIO in field operation. This solution is highly versatile and supports various test scenarios, including BIST and Scan Test, ensuring maximum test coverage. Additionally, this design requires only a single-ended PAD for signal transmission and testing. It simplifies the layout on board design, effectively reducing the number of PADs, which improves utilization. 

This architecture not only ensures efficient testing capabilities but also enhances testability and maintainability during the SoC validation phase:

• Testing: The High-Speed Test IO acts as a test port during manufacturing to channel up to 3GBPS data between ATE and SoC, helping with both bare die (wafer level) and package level testing
• Observation: The IO can be multiplexed as a high-speed clock observe on the Reference Validation Platform (RVP) board to observe the CLK 
• Power efficient mode: The same port is configured as a GPIO in production, with regular operating frequencies up to 200MHz supporting low power mode

Conclusion

As the complexity increases in SoCs, challenges in testing become essential to ensure functionality and high yield. ²ÝÁñÉçÇø High-Speed Test IO is an innovative IP solution designed to address high-speed, efficient testing of complex semiconductors by effectively utilizing the limited package pins to support high speed test as well as low power GPIO in production mode. This unique offering improves the testing time significantly and provides high throughput on advanced ATE testers, without involving complex interface protocols and while still meeting high-speed requirements. ²ÝÁñÉçÇø IO team is committed to support the High-Speed Test IO IP in advanced TSMC nodes. For more information, visit ²ÝÁñÉçÇø Foundation IP.