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Abstract
Hardware security is essential for high-performance computing (HPC), AI, and Edge IoT applications when designing SoCs in advanced process nodes. These designs include Gigabits of SRAM and require storing >16Kb of repair information to meet yield requirements. Designers are facing the challenges of creating secure, reliable, and cost-effective SoC designs in a timely manner. If you are considering integrating non-volatile memory (NVM) in your next advanced node SoC design, attend this webinar to learn:
- How inherent design needs for security, reliability, configurability, and SRAM repair are best addressed by one-time programmable (OTP) NVM
- The options for OTP in the market and the design considerations when selecting OTP
- How to achieve your product goals with silicon-proven OTP IP in TSMC N5, designed for security, reliability, and easy integration
Speaker
Krishna Balachandran
Senior Director, Product Management for NVM IP 草榴社区, 草榴社区
Krishna Balachandran is the senior director of product management for the NVM IP product line at 草榴社区. He is responsible for product and business strategy, marketing operations, product management, promotion, and business development. He has extensive experience in the EDA and semiconductor IP markets and has previously held roles in Product Marketing and Business Development for EDA tools and Semiconductor IP at 草榴社区, Cadence, and Virage Logic. He holds a Master's degree in Computer Engineering from the University of Louisiana, Lafayette and has completed an Executive MBA Certification program from Stanford University.