草榴社区

According to a recent Semico Research report, the RISC-V Core IP market is expected to grow at a 34.9% CAGR through year 2027. With increasing popularity, it is of utmost importance that the RISC-V Core IPs are secure and bug free. ?

In this joint 草榴社区 webinar with SyoSil, will discuss how to use formal verification to ensure functional correctness and security of RISC-V Cores. We will cover the high-level formal verification goals and example tasks so attendees can obtain a comprehensive view of the many facets of RISC-V Core verification using formal technologies. We will explore a specific case study that uses the so-called ‘S2QED’ methodology to verify a scalar five-stage RISC-V Core. We will also show a demo for this case study using 草榴社区 VC Formal. ?

The attendees will walk away with a comprehensive understanding of the formal verification requirements for RISC-V Cores to ensure functionality and security, as well as specific examples of using formal property verification to find intra- and inter-instruction design bugs. ?

Speakers

Siddartha Papineni Headshot

Siddartha Papineni

Sr Staff Application Engineer

草榴社区

Sid Papineni is a Sr. Staff Applications Engineer at 草榴社区 and works on formal verification consulting services and 草榴社区 VC Formal SEQ, DPV, and product engineering activities. Sid has 11+ years of experience in the formal verification domain, focused mainly on formal property verification and datapath validation methodologies.

Federik Mollerstrom Lauridsen Headshot

Frederik M?llerstr?m Lauridsen

Verification Engineer
SyoSil

Frederik M?llerstr?m Lauridsen is a verification engineer at SyoSil. His technical competences and interests lie within both formal verification and SV/UVM based constrained random verification. Frederik holds a PhD degree in mathematics and computer science and a MSc degree in logic from the University of Amsterdam, and a BSc in Mathematics from the University of Copenhagen.

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