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草榴社区 Webinar | Available On Demand
The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project stage multiplies the cost by ten. Bugs that escape verification and make their way to silicon are very expensive and time-consuming to fix. The ideal is to catch as many types of issues as early as possible while the designers enter the register transfer level (RTL) design and the verification engineers code the testbench in a hardware verification language.
Through this 草榴社区 webinar, we are going to demonstrate how design and verification iterations can be significantly reduced and major project milestones can be achieved substantially faster using the 草榴社区 Euclide integrated development solution. Additionally, the 草榴社区 webinar will showcase different SystemVerilog and UVM content assistance capabilities that can be leveraged by design and verification engineers to improve their coding productivity while improving simulation performance, synthesis compatibility.
Lastly, We will also touch upon a few case-studies highlighting actual gains realized by users with this solution.
Speaker
Eldon Nelson
Staff Application Engineer
草榴社区
Eldon Nelson is a Staff Application Engineer in the Verification Group at 草榴社区. He received his B.S. and M.S. degree in electrical engineering from the University of Minnesota and is a licensed Professional Engineer (P.E.). Before working at 草榴社区 Eldon worked for Intel, Micron Technology, IBM, Unisys, and the National Science Foundation. He has 6 published papers at DVCon and received the Best Paper Award at the conference in 2016. He held a variety of volunteer roles at IEEE and is now the Past Chair of the IEEE Twin Cities Section. He is based in Minneapolis, MN.