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The ability to mix and match multiple ISA extensions and add user-defined ISA extensions makes RISC-V verification more challenging than conventional processor verification. This ²ÝÁñÉçÇø webinar demonstrates the verification of standard RISC-V ISA extensions. A subsequent webcast will demonstrate custom ISA verification. The multiple ISA verification problem is solved by RISCV-DV with configurability for ISA specific test generation. RISCV-DV addresses the generation of ISA specific tests in one pass of simulation using ²ÝÁñÉçÇø VCS? as the efficient constraint solver for instruction generation using constraint random methodology. The tests consist of valid instruction sequences (programs) for the target ISA of the processor core under verification. The generated programs are run on the processor core simulated with ²ÝÁñÉçÇø VCS and the results are compared with Spike instruction set simulation (ISS) results.

This presentation will showcase: 

• A reference methodology for verifying a Bluespec RV32IMC MCU-X processor core based on RISCV-DV. 
• How designers can leverage ²ÝÁñÉçÇø VCS simulation and ²ÝÁñÉçÇø Verdi? for debug and relevant advanced coverage methodology, to help speed verification signoff.
• The combination of RISCV-DV and ²ÝÁñÉçÇø tools provides a powerful and flexible solution for RISC-V verification and highest coverage.
• Demo on the RISC-V verification solution on the ²ÝÁñÉçÇø Cloud platform.
   

Whether you are a chip verification architect or a verification engineer or a system designer, this ²ÝÁñÉçÇø webinar will provide valuable insights into how to set up a constraint random verification solution for a RISC-V processor to achieve the highest coverage.