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Continuous downscaling of the critical dimensions in semiconductor devices is the cornerstone of technological revolution. As the technology nodes keep shrinking, innovations in fabrication technologies are needed to continue the trend. We have arrived at the age where atomic level precision in the fabrication of semiconductor devices is needed to keep improving PPA. Thus, advanced film fabrication techniques that provide precise control over the thickness of the material being deposited or etched are crucial for the next generation of devices.

Atomic layer processing technologies such as atomic layer deposition and atomic layer etching are touted as the key technologies to propel thin-film fabrication at extreme limits. This white paper details an advanced atomic scale simulation approach to develop atomic layer etch processes by highlighting an application to silicon. The methodology is widely applicable to any reactant species¨Csurface combination. Such an approach can be used by process modeling engineers to test different process conditions for achieving maximum yield and avoid expensive experiments.