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²ÝÁñÉçÇø UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express and CXL. The IP enables latency-optimized NoC-to-NoC links with AXI, CXS, CHI C2C, and streaming protocols. The controller IP implements an RDI interface to the PHY and an FDI interface between the Die-to-Die Adapter and Protocol Layers. These interfaces include all the necessary sideband signaling for protocol discovery and negotiation between two dies, and smooth link initialization and operation. ²ÝÁñÉçÇø UCIe Controller IP offers maximum performance, minimum latency, and implementation flexibility. The IP ensures link reliability by supporting retry mechanism and performing CRC or parity checks for error detection. The flexible IP implementation targets single-module or multimodule configurations, both for advanced and standard packages. ²ÝÁñÉçÇø UCIe Controller IP along with ²ÝÁñÉçÇø UCIe PHY IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die designs. ²ÝÁñÉçÇø UCIe Controller IP along with ²ÝÁñÉçÇø UCIe PHY IP and Verification IP deliver a complete solution for die-to-die connectivity in multi-die designs.

²ÝÁñÉçÇø UCIe Controller IP Datasheet