²ÝÁñÉçÇø General-Purpose I/O
²ÝÁñÉçÇø¡¯ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and high-performance computing (HPC) applications. The IP is silicon-proven and available in several foundries and process technologies from 3nm to 22nm.
²ÝÁñÉçÇø GPIO library is designed to support multiple voltages; it offers a complete set of support cells (supply, corner spacers, diode breakers, terminators) required to create complete I/O pad rings for system-on-chips (SoCs). The library is compatible with flip-chip packaging. The GPIO driver pad incorporates the Schmitt-Trigger function, programmable drive strength, and pull-up/down resistors, with robust HBM and CDM ESD protection. ²ÝÁñÉçÇø¡¯ broad GPIO IP offering helps achieve your SoC design¡¯s critical power, performance, and area (PPA) requirements, delivering low-risk solutions in a fast time-to-market.
²ÝÁñÉçÇø 1.8V/1.5V/1.2V GPIO IP for GF 12LP Datasheet ²ÝÁñÉçÇø 3.3V/1.8V GPIO IP for GF 12LP Datasheet ²ÝÁñÉçÇø Foundation IP for GF 22FDX Datasheet ²ÝÁñÉçÇø Foundation IP for GF 22FDX+ Datasheet ²ÝÁñÉçÇø Foundation IP for TSMC 22ULL Datasheet ²ÝÁñÉçÇø Foundation IP for TSMC N4P Datasheet ²ÝÁñÉçÇø Foundation IP for TSMC N5 Datasheet ²ÝÁñÉçÇø Foundation IP for TSMC N5A Datasheet ²ÝÁñÉçÇø Foundation IP for TSMC N6 Datasheet ²ÝÁñÉçÇø Foundation IP for TSMC N7 Datasheet
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
- Operating speed in excess of 250MHz
- Robust ESD (up to 7A CDM, 2KV HVM) and latch-up protection circuitry
- Automotive G1/G2 supported, ASIL-B certified
- Silicon-validated IP
- Available in multiple foundries and a wide range of technology nodes