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The ²ÝÁñÉçÇø XAUI PHY IP is compliant with the XAUI specification and designed for use in any networking or high-end computing SoC solutions. Designed for high-speed backplanes, the XAUI PHY supports the 10 Gigabit Ethernet standards that are commonly used in high-speed communications applications. Based on ²ÝÁñÉçÇø' proven high-speed SerDes technology, the ²ÝÁñÉçÇø XAUI PHY IP provides a cost-effective and extremely low-power solution that is designed to meet the needs of today's XAUI designs.

To handle increasing communication system speeds, the XAUI standard is designed to take a 10 Gbps serial stream and divide into four 2.5 Gbps serial streams that run over copper traces and chip-to-chip connections using 8b/10b coding at 3.125 Gbaud. By taking advantage of copper links, higher-performance communications applications can be cost-effectively deployed.

The XAUI PHY integrates high-speed mixed-signal custom CMOS circuitry and is compliant with the XAUI base specification. While extremely low in power consumption and area requirements, ²ÝÁñÉçÇø' XAUI PHY IP substantially exceeds the electrical specifications in such key performance areas as jitter and receiver sensitivity.

The ²ÝÁñÉçÇø Ethernet IP solutions consist of configurable controllers and silicon-proven PHYs supporting speeds of up to 100G, verification IP, IP Prototyping Kits, Software Development Kits and Interface IP Subsystems.

²ÝÁñÉçÇø XAUI PHY Datasheet
²ÝÁñÉçÇø XAUI PHY for Common Platform Processes Datasheet