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Measure Timing Margin of Actual Functional Paths In-Test or In-Field

The Path Margin Monitor (PMM) solution consists of multiple PMM units, a PMM controller, and associated software and EDA automation. PMM IP is a building block for the PMM solution which is also supported by an automated implementation flow from ²ÝÁñÉçÇø. Path selection logic, RTL configuration and generation, connecting to functional and/or test paths, synthesis, implementation, timing validation and path qualification are the key functions addressed by the EDA automation provided. Associated software allows the data generated from the PMM solution to be effectively analyzed and allow precise decisions made based on those insights. The SLM PMM IP is also available as an ISO 26262 ASIL-B ready product.

Figure 1: ²ÝÁñÉçÇø Path Margin Monitor

Path Margin Monitor Unit

The PMM unit enables timing margin measurement of selected path in-test or mission mode. Timing margin is a key indicator of silicon structural health. Each PMM can handle multiple end points for measurement and each PMM controller can support multiple PMMs. On a single chip you can place numerous PMMs without much area overhead, providing very valuable data which can be analyzed for insights to optimize any phase of silicon lifecycle. EDA and software automation along with path selection logic plays a crucial role in making PMMs practical.

Path Margin Monitor Controller

Figure 2: ²ÝÁñÉçÇø Path Margin Monitor Controller

Use Cases