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²ÝÁñÉçÇø DDR5/4 Controller is a next-generation memory controller optimized for latency, bandwidth, and area, supporting JEDEC standard DDR5 and DDR4 SDRAMs and DIMMS. The highly configurable controller meets or exceeds the design requirements of a wide range of applications from data center to consumer. The ²ÝÁñÉçÇø DDR5/4 Controller connects to the ²ÝÁñÉçÇø DDR5/4 PHY or other PHYs via the DFI 5.0 interface to create a complete memory interface solution. The controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.

The DDR controller block includes advanced command scheduler, memory protocol handler, optional ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.

The ²ÝÁñÉçÇø DDR Controller seamlessly integrates the ²ÝÁñÉçÇø Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. ²ÝÁñÉçÇø Secure DDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the ²ÝÁñÉçÇø secure memory controllers is as low as 2 clock cycles.

Learn about the broad portfolio of Security ²ÝÁñÉçÇø for Interfaces.

²ÝÁñÉçÇø DDR5/4 Controller IP Datasheet