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Hybrid Architecture Lowers Area, Power and Reduces Routing Congestion

Interconnect Fabric implementations of the AMBA 3 AXI on-chip-bus protocol are designed to meet today's SoC's high performance requirements. While these implementations successfully achieve the performance goal they fall short in addressing the requirements of smaller area, lower power and reduced routing congestion. The feature of the ²ÝÁñÉçÇø Interconnect Fabric for AMBA 3 AXI enables the combination of dedicated high performance channels with lower performance shared channels. By eliminating redundant logic and wires designers are able to realize lower area, power and reduced routing congestion. The hybrid architecture provides a balance between area, performance and power which can be immediately utilized in native AMBA 3 AXI based design or in designs transitioning from AMBA 2.0 AHB. The new interconnect fabric architecture has been validated against the "AMBA 3 Assured" ²ÝÁñÉçÇø Verification IP ensuring adherence to the AMBA 3 AXI Specification. Automated configuration and assembly with ²ÝÁñÉçÇø' coreAssembler tool enables the IP to be rapidly deployed into the design environment.

Traditional AMBA 3 AXI architecture: consists of individual dedicated buses that service specific manager and subordinate devices

Advanced hybrid architecture for the AMBA 3 AXI interconnect: provides a choice of connecting the manager-to-subordinate link via a shared or dedicated bus within a single AMBA 3 AXI on-chip bus interconnect

Technical Overview

Up till now the standard AMBA 3 AXI interconnect fabric implementation only targets the high performance SoC requirement by offering a multiple address, multiple data architecture which supports parallel traffic from independent managers and subordinates. On a per port basis you have independent write and read, data and response channels resulting in this type of architecture being able to support even the most demanding system bus bandwidths requirements. While many component connections within a high performance SoC will require such a high bandwidth, there are also managers and subordinate connections which do not. For these system elements, a full multiple address multiple data architecture introduces a considerable amount of redundant logic which wastes die area, power and adds complexity to routing.

The new Hybrid feature of the ²ÝÁñÉçÇø Interconnect Fabric for AMBA 3 AXI provides designers with a configurable, optimized architecture enabling redundancy to be eliminated, bringing about savings in area, power and routing congestion. The Hybrid architecture features allows low performance manager subordinate links to be combined into single shared channels, eliminating the logic and wires associated with having dedicated channels for low performance managers and subordinates. Within a single instance high performance managers and subordinates can have dedicated high performance channels and combined shared channels for the low performance links. The hybrid architecture provides a balance between area, performance and power which can be utilized in native AMBA 3 AXI based design and also minimizes the impact to the design when transitioning from an AMBA AHB based architecture to a pure AMBA 3 AXI based architecture. The new interconnect fabric architecture has been validated against the "AMBA 3 Assured" ²ÝÁñÉçÇø Verification IP ensuring adherence to the AMBA 3 AXI Specification. The AMBA 3 Assured logo indicates that the Verification IP has been shown to correctly implement the AMBA 3 AXI specification, as defined by the assertion-based AXI protocol rule sets available from ARM. The Verification IP monitor also facilitates protocol coverage collection and provides statistics on bandwidth and latencies on a per channel basis. Automated configuration and assembly with ²ÝÁñÉçÇø' coreAssembler tool enables the IP to be rapidly deployed into the design environment.

Availability

The Hybrid Architecture Feature of the ²ÝÁñÉçÇø Interconnect Fabric for AMBA 3 AXI (DW_axi) is available on a pay-per-use basis as part of the ²ÝÁñÉçÇø Cores AMBA Fabric license package. For information on ²ÝÁñÉçÇø IP solutions for the AMBA interconnect click here.

²ÝÁñÉçÇø IP ²ÝÁñÉçÇø for the AMBA Interconnect
Reduce Power, Area and Routing Congestion - Analysis of a High-Performance On-Chip-Bus Interconnect