草榴社区 ARC-V? RMX-500 Processors are based on the RISC-V instruction set architecture (ISA) and optimized for use in embedded applications where power & performance efficiency are key concerns. The DSP enhanced implementation (RMX-500D) adds DSP capability for applications such as IoT wearable devices where the combination of low power and signal processing are required to enable device performance and extend battery life.

The processors feature an efficient 5-stage Harvard architecture pipeline that provides excellent throughput for embedded applications.

The ARC-V RMX-500 features up to 64KB of Level 1 (L1) instruction & data cache and up to 2MB each of closely coupled instruction and data memories (CCM), maintain high code density and offer excellent performance within a very small footprint.

The DSP-enhanced RMX-500D cores include an optimized DSP implementation that features support for fixed-point DSP datatypes and vector operations.

To enable easy DSP software development, the ARC MetaWare Development Toolkit features a rich DSP software library and the included C/C++ Compiler supports commonly used DSP datatypes for easy algorithm programming. To maximize PPA of ARC-V RMX Processor-based designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.

草榴社区 ARC-V RMX-500 Block Diagram

草榴社区 ARC-V RMX-500 Series Datasheet

Highlights

Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
RISC and RISC + DSP 32-bit processors for low-power embedded applications (RMX-500D)
2x 32-bit DSP instruction extensions (RMX-500D) for fixed point and vector operations DSP extension instructions overlayed on RISC-V Vector Specification 1.0
Easy programming support with MetaWare C/C++ Compiler
Feature-rich DSP software library for easy algorithm programming (RMX-500D)
High degree of configurability
Support for custom instructions
Support for up to 64KB of L1 instruction and data caches
Support for up to 2 MB of closely coupled instruction and data memory and direct mapping of peripherals
Native Arm AMBA? AHB?, AHBLite? and AXI interfaces
Optional single and multicycle multiplier
ECC/Parity support
RISC-V AIA compatible interrupt handling architecture supporting up to 1023 direct message or wired interrupts
Advanced Platform Level Interrupt Controller (APLIC) with low latency network
N-Trace real-time trace debugging features