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The ²ÝÁñÉçÇø ARC-V? RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern. The DSP enhanced implementation (RMX-100D) adds DSP capability for applications such as hearable devices where the combination of low power and signal processing are required to enable device performance and extend battery life.

The ARC-V RMX-100 processors are based on the RISC-V instruction set architecture (ISA) and feature a balanced 3-stage Harvard architecture pipeline that provides sufficient throughput. The ARC-V RMX-100 features up to 64KB of level 1 (L1) instruction cache and up to 2MB each of closely coupled instruction and data memories (CCM).

The DSP-enhanced RMX-100D cores include an optimized DSP implementation that features a power-efficient unified 32x32 MUL/MAC unit and support for fixed-point DSP datatypes and vector operations. To enable easy DSP software development, the ARC MetaWare Development Toolkit features a rich DSP software library and the included C/C++ Compiler supports commonly used DSP datatypes for easy algorithm programming. The ARC-V RMX-100D processors maintain the high code density and offer excellent DSP performance within a very small footprint.

To maximize PPA of ARC-V RMX Processor-based designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.

²ÝÁñÉçÇø ARC-V RMX-100 Block Diagram

²ÝÁñÉçÇø ARC-V RMX-100 Series Datasheet