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The ²ÝÁñÉçÇø AHB DMA controller is a highly optimized centralized DMA IP component offering configuration of up to 8 channels each with dedicated channel buffers. The ²ÝÁñÉçÇø AHB DMA component can be configured and instantiated into the subsystem using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by ²ÝÁñÉçÇø Verification IP, thus reducing the time to first simulation.

The ²ÝÁñÉçÇø AHB DMA component for AMBA is available in encrypted format as part of the DesignWare Library. RTL source code is available for license separately, on a pay-per-use basis as part of the ²ÝÁñÉçÇø AHB DMA Controller license package.

A flexible, Multi-Channel, Multi-Interface, Centralized AHB DMA Controller (View Product Details for DW_ahb_dmac)

• Configurable selection of up to 8 DMA channels width dedicated channel buffering
• Up to 4 AHB manager interfaces with support for operation across multiple AHB layers
• Flexible handshaking options, software based, hardware based or peripheral interrupt based
• Features for improved bandwidth utilization e.g. bus locking, interface locking, fifo level mode
• Dedicated AHB subordinate interface for programmable DMA control
• Ability to allow source, destination or DW_ahb_dmac to enforce flow control
• Powerful address generation options e.g. multi DMA blocks, linked lists, auto channel register reloading

Verification IP for AMBA 2 AHB

²ÝÁñÉçÇø Verification IP integrates easily into Verilog, SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.

²ÝÁñÉçÇø IP ²ÝÁñÉçÇø for the AMBA Interconnect