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Introduction

Every milliwatt of power matters, regardless of the application. Designers can no longer wait for the final netlist to get accurate power numbers, as full visibility is needed as soon as RTL coding starts, when the most rewarding modifications can be made. At smaller technology nodes, dynamic power is becoming increasingly more dominant and the reduction of overall activity has become a necessity. As designs become vastly larger, designers need a tool that pinpoints the major power gluttons while suggesting modifications with the highest ROI.

Features and Benefits

• Integrated solution covering all aspects of power analysis including early RTL estimation and exploration
• Input agnostic
  • Works at RTL or gate-level
  • Supports dynamic activity through FSDB, VCD and SAIF
• Proven accuracy of power estimation through a calibration toolbox and use of existing data from reference design
• Various actionable profiling metrics such as Clock Gating Ratio (CGR) and Clock Gating Efficiency (CGE)
• Wide breadth of power exploration techniques including fine and coarse grain clock gating, micro-architectural modifications and memory access optimization
• Integration with Verdi? HW/SW Debug for multi-scenario Clock Gating Efficiency analysis and improvement
• Complementary to downstream implementation tools as it prepares RTL for better inferred clock gating during synthesis
• RTL signoff solution (power budget and CGE efficiency)