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Technology experts from 草榴社区 are presenting multiple topics at GOMACTech 2024 to help you build mission-critical, high-performance, low-power and trusted systems. Wherever your interest focuses, from the embedded edge to the data center, 草榴社区 experts can help you optimize your chips, systems and security to meet mission requirements.
AI Optimized Design
Migrating a 28GHz 5G mmWave PA from GF 45RFSOI to 22FDX Technology Using an AI-Driven EDA Platform
Gaurav Singh, Keith Lainer, Paul Colestock
SESSION 29.4?RF Tools for Modeling, Analysis, and Fabrication
While AI/ML approaches have been?shown to be successful for?FinFet?based logic migration, little has been published on?migrating Analog/RF between device technologies and technology nodes.? This task is exacerbated by the?uniqueness of different CMOS analog/RF foundry technologies.??In this paper, we propose a unique?Artificial Intelligence (AI) based approach that enables fast migration of leading-edge?Analog/RF designs between advanced specialty technology nodes. The novelty of this?paper is that it demonstrates RF design migration across both device type (PDSOI/FDSOI) and technology (high resistance/bulk). It also demonstrates a more design efficient method that delivers the same or better performance.
RF and Image Signal Processing
Scalable Compute Platform for Sensor Processing
Ian Land, and Michael Parker (RTX)
POSTER
DoD applications must continue to push the state-of-theart (SOTA) SWaP while advancing system performance for sensor processing. A scalable Vector Processor (VP) based compute platform can be created to deliver ASIClike performance/power while incorporating FPGA-like hardware flexibility. This paper presents a study of key processors and assesses the strengths and challenges where a vector-engine based platform can deliver capabilities beyond the traditional methods that leverage FPGAs, while adding in AI acceleration and considering multiple sensors, sensor fusion, and strategic applications.
Multi-Die Systems
Virtual Prototyping for Early Architecture Design Optimization of Multi-Die Systems
Tim Kogel, Holger Keding, Kamal Desai??
SESSION 1.2 Advances in Multi-chip Integration
Thermal Challenges of DoD 3D Heterogenous Integration
草榴社区: Rob Aitken, Ansys: Norman Chang, Len Orlando, Lang Lin
SESSION: 17.1 Thermal Technologies
2.5D, 3D, and 3DHI multi-die systems have emerged in response to the economic and technological challenges that are threatening the efficacy of Moore’s law. Importantly, multi-die systems facilitate the creation of variants that can be designed to enable a portfolio of low cost, flexible custom or semi-custom solutions. There are a host of considerations for these multi-variant multi-die systems, including the different ways to realize the interfaces to the choices of protocols, system pathfinding for die and chiplet placement, optimal memory utilization and coherency, and power and thermal management.
This paper discusses current state of the art, architectural challenges, and the direction of our project to use virtual prototypes for early quantitative architecture analysis. We will present a case study. This project aims to enable system architects to navigate complex design spacesand to shorten the time to market of multi-variant multi-die systems that meet power, performance, function, cost, and thermal requirements.
Ansys and 草榴社区 are commercial software companies that develop semiconductor solutions to enable their customers to achieve first pass success in the development of microelectronic systems. Within the commercial marketplace they provide complimentary solutions, that when used together, scale from chip, package, board, system, and systems of system; across the total lifecycle of electronic systems; the environments they operate in; and in the development of digital twin ecosystems. Both companies have a common footprint within both commercial and federal, aerospace, and defense industries which enables a unique perspective to identify overlapping technologies that benefit either industry.
Explored in this paper is the comparison and contrasting of DoD and commercial opportunities in the development of leap-ahead fine grain thermal aware place and route technologies to map capability and function to a multi-tier volume to achieve adversarial overmatch.
Secure Microelectronics Design
T-PROP Project: Assessing Hardware Confidentiality and Resiliency with RTL Simulation
Arturo Salz and Saurin Shroff
POSTER
Toward Assurance of Microelectronics 3rd Party IP – Looking a Gift Horse in the Mouth
Mike Borza, Dale Donchin, Robert Freeman, Alessandra Nardi, John Sorebo, Zongyao Wen
POSTER
After a VLSI design is completed and a file representing the physical design is delivered to a foundry for fabrication, substantial data processing such as Optical Proximity Correction (OPC) is performed. The transmission, storage, and transformation of the design data during manufacturing opens up several points of attack for a malicious actor to degrade or alter the design. Potential consequences could include unintended functionality, reduced yield, or reduced performance. This paper provides a description of the data flow from an initial physical design through the photomask fabrication process. It identifies attack points where a malicious actor could damage the integrity of the design. It then evaluates strategies to mitigate risks of successful attacks, as well as improving traceability to identify the point sources of attacks.
The potential to use embedded sensors and supporting infrastructure to detect hardware security attacks is a good use of existing device- and system-level information sources embedded in an SoC (system on chip). These integrated circuit package-level sensors and monitors have been available for some time, but their application emphasis has usually been on performance, reliability, and safety. By coupling existing and novel sensor technology with in-system and cloud-based analytics, it is possible to detect and mitigate the efforts of hardware hackers as they try to apply their skills to uncover the secrets and capabilities stored inside today’s advanced electronics. This paper will review sensors and supporting infrastructure and their capabilities to help detect and mitigate a security breach.
Formal Verification for Building Secure Hardware Systems
Naiyong Jin, Sudipta Kundu, Sean Safarpour, Manish Pandey
POSTER
Secure hardware is the foundation demanded by mission critical applications such as automobile ADAS, medical control systems and public infrastructure for power and water. Such systems rely on secure designs, where there are no unexpected or unauthorized ways to read or modify data such as private keys, encryption keys of privileged memory regions that are considered secure. Typical verification approaches based on code review and simulation are not sufficient to ensure unauthorized reads or accesses do not occur under all conditions. This requires formal verification. VC Formal Security Verification (FSV) app is the industry’s highest capacity automated formal verification solution to address this problem. FSV models a secure system as one that has the non-interference property[1] which holds if and only if any sequence of non-secret inputs will produce the same values at observing wires, regardless of what the values of secret wires are. In practice designs have various security zones and the user wants to find information flow between different pair of zones (disallow secure to unsecure, allow others). Intuitively, this problem can be formulated as marking a set of secret wires (a security zone) with a color ‘and checking whether the color propagates to the specified observing wires (destination) of the design. A typical industrial design has hundreds of such properties, and FSV parallelizes the formal verification of these properties for efficient security verification and has successfully verified the security of several state of the art industrial RTL designs.
Highly Secure Central Repository Framework for Complex RTL SoCs
Khushboo Mittal, Naincy Katyal, Nitin Garg, Dale Donchin Adam Cron
POSTER
Modern system-on-chips (SoCs) have increased vulnerabilities because of growing global supply chains, making it more challenging for design foundries to securely rely on IP designs from around the world. Further, making the appropriate IP choices and IP configuration decisions that may satisfy SoC requirements requires high level SoC design expertise. The complexity here comes from the fact that IPs can originate from several manufacturers and that each IP can have hundreds of settings without any knowledge of Power, Area, Speed, or Security (PASS). It is crucial to develop a strategy that can address design complexity and Secure RTL IP selection at the same time due to the short time to market and increasing design difficulties. To address these issues, this paper proposes a secure central repository (repo) framework where authorization is granted through a security asset container mechanism and it further provides a systematic method for authorized IP authors to store IP metadata, such as PASS, IP version, and legitimate RTL sources, in a secure manner.
Space and Extreme Environment Design
The Case for COLD and CRYO CMOS & FD-SOI
Jamil Kawa and Steve Whiteley
SESSION 44.5 Superconducting and Cryogenic Technology
CMOS has been proven to work down to sub 1oK and FD-SOI based Gate Arrays that are at the heart of Quantum Computing control blocks operating below 4oK. With the era of Big Data and Big Compute already with us, COLD CMOS computing farms operating in a liquid Nitrogen cooled environment offer very compelling power-performance benefits. And in space-based applications where power budgets are extremely stringent, CRYO CMOS optimizations are a natural fit.
However, there is more to COLD and CRYO CMOS & FD-SOI than better performance at lower power. Issues associated with device re-engineering, finding the optimal combination of power supply voltage reduction and the “equilibrium” temperature of operation for optimal cooling power savings, and of device variability at reduced temperatures must be addressed thoroughly.
In this talk we will address the issues and benefits of CMOS and FD-SOI retargeted for cooled compute environments, quantum controller environments and space-based applications. We will draw on our efforts in the DARPA sponsored LTLT program as well as 草榴社区’ overall research and activities to advance the state of the art in COLD CMOS.
Leveraging Automotive Functional Safety Design Techniques for RHBD SoCs
Jeff Wetch and David Kingston
POSTER
The automotive industry has introduced many functional safety constructs into their SoC designs for many years that enhance the fault tolerance and safety of their electronics systems. These include fault tolerant state machines, triple mode redundant storage elements, error correction for memories and many others. Many of these same constructs can be used in radiation hardened SoCs to mitigate the effects of heavy ions and particle strikes on the die.
Single event effects (SEUs) in integrated circuits can be mitigated by careful layout of the various standard cells in a library used for synthesizing SoCs and by taking advantage of the pre-defined functional safety (FuSa) constructs already available to automotive SoC designers. This paper will discuss the various techniques available to engineers for insertion of flip-flop storage elements based on the soft error rate (SER) of individual flip-flop library cells.