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Location: GAMR 1

Multi-die design has become commonplace in many applications such as high-performance computing, networking, automotive, and mobile. Since multi-die designs involve multiple chiplets, designers must have both a chiplet-level and a?system-level view at all times.? A typical design example shows how this works.? The process starts with early architecture exploration which benefits greatly from the bridging of functional and physical architectures. It continues to design implementation with thermal, signal and power integrity analysis occurring at both chiplet and system-level.? Finally, signoff includes the integration of the chiplets and the analysis of the full design so it is ready for testing and manufacturing.

Location: GAMR 1

Multi-die verification requires more than just traditional simulation, emulation, and prototyping techniques. It is not enough to make a monolithic model of the design, combine it with testbenches for dynamic execution, and add hardware assist to increase speed.? Due to their large complexity, monolithic models of multi-die design can lead to cumbersome, hard to manage set-ups. ?A modular hardware-assisted approach is a more effective solution.? It starts with the development of prototypes and emulation models for a single die.? The next step is to configure the model for single-die or multi-die execution, effectively applying multi-die integration to the verification process. User results show much faster verification and validation and lower demand for computing and storage resources.

Location: GAB J

Location: GAMR 3

Location: GAMR 1

Adopting AI and machine learning capabilities in EDA tools can make them run faster and produce better results for tasks ranging from early architecture exploration to design implementation and system signoff. For example, AI can improve early architecture exploration by automating the setup and execution of scenarios and quickly obtaining optimal power and performance results. An AI-enabled system optimization flow for thermal, signal and power integrity can expedite floorplanning and implementation.? Results from a recent CoWoS design show the advantages.

Location: TBA

Location: GAB J

Chiplet design has led to many new issues, including: Producing full concurrent workflows for all stages of development from partitioning through packaging, test, integration, and manufacturing. Creating building blocks that can be simply dropped into other designs or even sold on the open market. Choosing the best die-to-die interface to handle connections inside the package. The interface must be extremely fast with low latency, occupy little chip area, and add little to power or thermal budgets. The leading contenders are BoW (Open Compute Platform) and UCIe (UCIe Consortium). The session will focus on major challenges, typical ways to resolve them, and current status of the resolution process.

Location: Ballroom H

Advanced packaging for multi-die designs provides higher performance, smaller footprint, and increased functionality while reducing system power. ?However, it also introduces new complexity due the integration of multiple chiplets into a package.? New tools and design methods are necessary to handle this complexity.? A holistic system-level co-design and co-verification approach can ease heterogeneous integration and improve productivity. ?It covers tasks such as automated routing, bump counts, traces and signals, silicon/package co-design, and multi-physics simulations. ?In practice, designers will also need to collaborate closely with packagers and foundries to achieve silicon success without lengthening time-to-market.

Location: Ballroom H

Multi-die designs consist of an array of heterogeneous dies, or chiplets, optimized for each functional component. They offer new levels of flexibility and system power and performance, but they also introduce much greater design complexity. ?And, of of course, validation and verification become more difficult as well.? The key verification and validation elements required for successful multi-die designs include protocol solutions, system verification and convergence, a software-first approach using hardware-assist, and a modular approach to system bring-up.? As one might expect, the added complexity leads to longer run times, more complex debugging, and extended time schedules.?

Location: GAMR 3

Location: GAMR 3