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Overview

²ÝÁñÉçÇø Verification IP is architected to address the challenges of SoC verification and offers a broad portfolio of interface and memory VIP. ²ÝÁñÉçÇø Verification IP, based on a native SystemVerilog UVM architecture, is simple to integrate into any SystemVerilog UVM testbench environment. To accelerate coverage closure, each VIP includes built-in verification plans, built-in functional coverage and sequence library source code. For improved debug, it is integrated with ²ÝÁñÉçÇø¡¯ unique protocol-aware debug environment, Verdi Protocol Analyzer, which gives users a high-level view of the protocol from which they can easily navigate through the protocol hierarchy from the high-level transactions and transfers to the low-level object field values.

Since the announcement of the native SystemVerilog architecture in 2012, the ²ÝÁñÉçÇø Verification IP portfolio has rapidly expanded to encompass titles needed for SoC verification including on-chip buses and off-chip interfaces: AMBA? 4, AMBA 5 CHI, OCP 3.0, PCI Express (4.0 through 1.0), Ethernet (up to 100G), MIPI (multiple titles), HDMI, SATA, SAS, I2C, I2S, UART and USB. In addition to broad customer usage on a wide range of IPs and SoCs, the VIP is used and tested with DesignWare IP to simplify customers¡¯ connectivity and integration testing.

The ²ÝÁñÉçÇø VIP portfolio is being continually enhanced and expanded, most recently with the addition of the latest JEDEC memory standards to provide a complete solution for SoC verification and with the addition of test suites for block-level verification. In addition to this the portfolio has also been enhanced to include PCI Express 4.0, HDMI 2.0 and HDCP 2.2.

Memory VIP for JEDEC Protocol Verification

²ÝÁñÉçÇø Memory VIP is available now and supports DDR4, DDR3, LPDDR3 and LPDDR2 protocols. LPDDR4 is also available to customers seeking collaboration on early access. The memory VIP may be used to verify memory controllers at the block-level by providing coverage and checking of the JEDEC standards. Verification features include back door access to the memory that supports file read, file dump, pattern initialization and ¡°peek and poke¡± of memory contents. In addition to JEDEC protocol verification, the memory VIP can be configured to model any individual memory components. This enables engineers to verify their SoC¡¯s interaction with specific memory components that will be used in their end product. It includes built-in support for RDIMM and LRDIMM packages.

The memory VIP uses the same SystemVerilog-based architecture as the ²ÝÁñÉçÇø interface VIP with specific enhancements to support memory activity. It offers the same advantages in SystemVerilog UVM environments for ease of use, ease of integration and debug. The ²ÝÁñÉçÇø memory VIP titles do not require wrappers, translators, or remapping, and support all major simulators.

²ÝÁñÉçÇø memory VIP is integrated with ²ÝÁñÉçÇø¡¯ protocol-aware debug environment, extending the functionality of Verdi Protocol Analyzer to support memory-centric debug features. Protocol Analyzer enables users to quickly understand memory activity, identify bottlenecks, and find and debug unexpected behavior. It provides a complete view of the memory array which can be scrolled in the time domain to show memory values at a specific point in time and the last action on those memory locations ¨C read, write, peek, poke, and more, as shown in Figure 1.

VIP Support for New Protocols

• PCI Express 4.0: ²ÝÁñÉçÇø¡¯ PCI Express VIP is based on its native SystemVerilog UVM VIP architecture. It has been used extensively for verification of PCIe 1.0/1.1, 2.0/2.1, and 3.0 designs and is enhanced to support PCI Express 4.0. The PCIe 4.0 capability is available as an early technology and is being used by early adopters based on revision 0.3 of the specification. The model fully supports the 16 GT/s speeds along with built in sequences for all three phases of equalization and control of coefficients. Built-in checks validate the protocol while providing testbench accessible statistics. PCI Express 4.0 VIP will be available as a separate license to PCIe titles owners and included as part of the ²ÝÁñÉçÇø VIP Library and Verification Compiler.
• HDMI 2.0: Extending the already successful HDMI VIP and based on ²ÝÁñÉçÇø¡¯ proven SystemVerilog UVM VIP architecture to support HDMI 2.0 and HDCP 2.2. The latest specification support for HDMI is available to all current HDMI licensee owners. HDMI VIP is included as part of ²ÝÁñÉçÇø¡¯ VIP Library and Verification Compiler.

Test Suites

Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. To support designers in this challenge, ²ÝÁñÉçÇø is adding test suites to its major VIP titles. ²ÝÁñÉçÇø Ethernet VIP, supporting 10/100/1G/10G/40G/100G, is now provided with a UNH test suite of directed tests that span normal data exchange cases, error injected cases, and corner case scenarios to help test the DUT for a wide spectrum of scenarios. The test suite is provided in source code to ease integration and enable re-use across multiple projects. The test suite is a complete self-contained and design-proven testbench that helps eliminate the task of writing compliance tests. Source code of the test suite is available for download to all Ethernet title, ²ÝÁñÉçÇø VIP Library, and Verification Compiler owners.

For additional information about test suites for USB, PCI Express, MIPI and AMBA, please contact your local sales office.

All Memory VIP, Interface VIP and test suites are included in the ²ÝÁñÉçÇø VIP Library and Verification Compiler.

Visit synopsys.com/vip to see the full scope of ²ÝÁñÉçÇø VIP portfolio.