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Multicore Design Using ASIPs: Blending Performance and Efficiency with Programmability
By Markus Willems, Sr. Product Marketing Manager, Processor 草榴社区, 草榴社区
In the early 2000s, analysts warned about a looming complexity crisis in ASIC design. It was forecast that by 2006, designers would no longer be able to make effective use of the abundant logic-gate counts promised by new process technology nodes of 90 nanometer (nm) and beyond. Yet new generations of SoCs have emerged for all kinds of systems, from wireless communicators over multimedia devices to automotive systems. The industry has responded to the complexity threat by an increased use of semiconductor IP and programmable processor cores.
The traditional SoC approach saw the use of standard microcontrollers and eventually DSPs, while offloading performance or power-critical functions into specialized fixed-function accelerators. Moving such functions into these accelerators comes with a heavy cost: loss of programmability, and therefore loss of flexibility after manufacture. This is intolerable with advanced process technology nodes, where high mask costs necessitate the reuse of silicon in multiple products and product generations to expand the revenue lifetime of an SoC.
As a result, there is a trend towards the use of heterogeneous multicore SoCs, which feature a range of very specialized processor cores with architectures and instruction-sets optimized for a certain application: application-specific instruction-set processors (ASIPs). ASIPs fill the architectural spectrum between general-purpose programmable processors and dedicated hardware or fixed-function cores by enabling designers to effectively combine high flexibility through software programmability with high performance efficiency (high throughput and low energy consumption). Figure 1 illustrates this concept for wireless baseband chips, where multi-ASIP cores enable software defined radio.
Figure 1: Evolution of wireless baseband chip
What is an ASIP?
An ASIP combines a software programmable processor and application-specific hardware components, with its architecture optimized for the set of functions that it has to implement, with some margin for algorithmic evolution. The instruction-set architecture (ISA) is tailored for the efficient implementation of the selected functions, while still providing enough flexibility to change the operation modes in software. The efficient implementation requires an inherent parallelism of functional units. Due to their architectural specialization, combined with instruction-level and data-level parallelism, ASIPs can offer performance and energy characteristics that are superior to general-purpose processors and close to fixed-function custom logic implementation. ASIP software programmability offers the flexibility to address multiple algorithmic standards and evolving specifications. This increased flexibility allows for reuse of both IP blocks (in different SoCs) and SoCs (in different products), which often drives the financial success of entire development teams.
ASIPs can cover a wide range of processor architectures, from configurable customizable processors with relatively high flexibility to programmable datapaths with relatively low flexibility but higher energy efficiency, as shown in Figure 2. Designers can choose the optimal ASIP architecture that best fits the implementation of the algorithm(s).
Figure 2: ASIP application flexibility and performance efficiency
ASIP Application Domains
ASIPs have found their way into almost any application domain that requires both high performance efficiency and flexibility. This is due to the fact that an ASIP architecture is not limited to use a processor template, but offers full architectural freedom to meet domain-specific requirements. Examples include high-performance portable audio devices and hearing aids with highly specialized data types and memory configurations, wireline and wireless modems that call for highly specialized matrix processing support, vector-based image and vision processing, and specialized yet programmable accelerators for network processors, to name a few.
草榴社区 ASIP Designer: Efficient Design and Programming of ASIPs
Notwithstanding their technological advantages, it is sometimes argued that the adoption of ASIPs can be risky for a variety of reasons. Perceived risks include the extra time needed to design the architecture and the RTL implementation, potential reliability issues resulting from the introduction of new hardware, and the difficulty of programming ASIPs due to a lack of software development tools. A tool-based ASIP design flow, as enabled by 草榴社区' ASIP Designer (Figure 3), overcomes these potential issues.
Figure 3: ASIP Designer Tool Flow
ASIP Designer brings ASIP design within easy reach of every SoC team. At the heart of the ASIP design flow is the processor specification in nML, a hierarchical and highly structured architecture description language that is used to represent ASIP designs at the abstraction level of a programmer's manual. nML is used to model an ASIP architecture in a concise way, defining both the structural characteristics of the design as well as the instruction set architecture.
The language based approach enables users to explore multiple processor architecture alternatives in minutes. Using the nML description, the tool automatically generates both the synthesizable RTL of the processor and an SDK that includes an optimizing C/C++ compiler, instruction set simulator, linker, assembler, software debugger and profiler. The tool ensures consistency of the hardware and the SDK at all stages of the design process.
The patented compiler generation technology includes an LLVM compiler front-end and support for the OpenCL kernel language. Immediate availability of the compiler enables users to run their C, C++ and OpenCL application code on the automatically-generated instruction-set simulator as soon as the nML-based description is available. With this unique 'compiler-in the-loop' approach, as well as the extensive profiling capabilities of the debugger, ASIP Designer users can rapidly analyze and explore ASIP architectures and instruction sets to find the optimal power and performance design points for their target application.
Summary
Modern SoCs integrate dozens of complex system functions, each requiring its own optimal balance of performance, flexibility, energy consumption, communication, and design time. The traditional model of a (configurable) general-purpose processor core with a number of fixed hardware accelerators is no longer sufficient to meet design and time to market goals. ASIPs can offer the best balance for each system function, forming the basis of new generations of multicore SoCs. An effective ASIP design approach will support a broad range of architectures, from highly flexible configurable processors to less flexible programmable datapaths that provide higher energy efficiency. ASIP design requires tools and methodologies, such as those available with 草榴社区' ASIP Designer tool suite, that enable fast architectural exploration, hardware synthesis, software compilation, inter-ASIP communication, and verification.
For more information on ASIP Designer, visit www.synopsys.com/ASIP