草榴社区

In an era of advanced deep submicron technologies, we can no longer ignore what’s happening inside our chips. We must monitor the condition of the silicon, test for proper operation, and repair in the field whenever possible. This places huge demands on the process of Silicon Lifecycle Management (SLM), and an in-chip monitoring solution to support optimal device results. This article outlines the most important requirements for a complete Monitor, Test and Repair (MTR) IP solution for today’s large and complex semiconductor devices and offers solutions available from 草榴社区 to help meet such requirements.

There is a need for highly reliable silicon throughout the full lifecycle, from design through manufacturing and in-field deployment, to end of life. The requirements for reliability are driven by increased susceptibility to voltage and temperature variations, higher risk of thermal issues, and more complex manufacturing processes.

Many applications, including automotive and military-aerospace (mil-aero), subject electronics to harsh environmental conditions. Chips must survive extreme temperature, humidity, vibration, and radiation, all of which can diminish performance and reliability. SoCs are pushed for ever more compute performance and workloads, placing them under additional stress that can cause them to age and fail sooner than expected.

It is imperative that chips operate in ways that do not compromise reliability. Ensuring reliability is one of the most important goals of a complete SLM solution.

Figure 1 illustrates the full scope of the 草榴社区 SLM solution, from design through in-field analytics. This entire process relies on in-chip process, voltage/glitch, and temperature (PVT) monitors to provide feedback at every lifecycle stage for visibility into what is happening within the chip. The data collected from the monitors must be analyzed and stored for further analytics that cover both the history of each device and the history of the “fleet” of chips deployed in the field. These insights enable many benefits, including better design, optimized manufacturing, better yield, and longer in-field reliability. 

The process of using 草榴社区 in-chip SLM PVT IP can be summarized into four steps:

• Monitor: Embedded monitors and other SLM structures are integrated early in the design stage
• Transport: Data from the monitors is gathered and transported to an SLM database
• Analyze: The monitor data is analyzed throughout the device lifecycle
• Act: Based on the analysis, insightful decisions are made in real time at any lifecycle stage

Since the monitors drive the entire four-step flow, a wide variety of embedded PVT IP is needed to achieve all the desired benefits. The types of IP required fall into three general categories. 

The first category is environmental IP, designed to measure the health of the silicon given the harsh conditions found in many applications. PVT monitors and sensors gather fundamental metrics about the silicon operating environment.

The second category, structural SLM IP is a broad category, including signal integrity monitors that check die-to-die signal quality and path margin monitors (PMMs) for tracking delays along logic paths. PMMs are especially valuable since degradation in timing is often an indicator of silicon issues due to aging or environmental conditions. The 草榴社区 Self-Test and Repair (STAR) Memory System? is a fully automated solution to test, repair, and diagnose embedded memories. Additional monitors support built in self-test (BIST) techniques to check proper functional operation.

The challenges of SLM are particularly acute for 3DIC and other multi-die devices. The dies, also called chiplets, may be fabricated using diverse technologies with different aging effects and failure modes. Advanced packaging techniques, such as silicon interposers and organic substrates, introduce new manufacturing complexities and the connections between the dies create additional possible points of failure. The industry has come together to introduce the Universal Chiplet Interconnect Express? (UCIe?) standard, which standardizes 2.5D die-to-die connectivity. 草榴社区 provides SLM IP for UCIe Monitor, Test, and Repair (MTR). 

Another specification relevant to die-to-die interconnect is the IEEE 1838 Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits. 草榴社区 SLM IP supports this standard, able to test both individual dies and die-to-die interconnects. An at-speed inter-die lane MTR flow enables reconfiguration and repair using redundant lanes. The flow supports both logic-to-logic interconnects and logic-to-memory interconnects, complaint with the physical (PHY) layer such as double data rate (DDR) and High Bandwidth Memory (HBM).

The final category is SLM functional monitor IP. Clock and delay monitors (CDMs) measure the delay between edges of one or more signals, enabling clock duty cycle quality checks, memory access time tracking, and digital delay line test characterization. Finally, High Speed Access & Test IP (HSAT) enables adaptive high bandwidth testing over existing functional interfaces. Figure 2 summarizes the available 草榴社区 SLM IP in all three categories. 

It takes more than a portfolio of IP, however broad, to provide the comprehensive SLM solution shown in Figure 1. The insertion of the SLM IP into the design, the integration into the test flow, the collection of data in the SLM database, and the analytics at every stage require advanced electronic design automation (EDA) software as well. 草榴社区 provides all the capabilities needed, with support for SLM IP incorporated into the 草榴社区 TestMAXTM ALE, 草榴社区 Avalon, 草榴社区 SysNav, and 草榴社区 Silicon.da products. 

Combining the rich portfolio of 草榴社区 SLM IP with the 草榴社区 SLM software solutions enables the best industry support for management of chips throughout their entire lifecycle. These pieces fit together for a complete solution at the system on chip (SoC) and multi-die levels. Figure 3 shows a possible SoC with many SLM IP elements, connected to a wide range of analytics. Transporting data to the cloud enables AI-driven fleet level analytics, including predicting field failures based on results from many similar devices.

There is little argument in the industry that SLM must play an ever-larger role at every stage of the silicon lifecycle. Every aspect of modern chip technology offers more opportunities for reliability issues to arise over time while, in parallel, end applications demand more reliable chips. Only the visibility and insight provided by a complete SLM solution can address these challenges. SLM can extend the life of the SoC by detecting issues and taking meaningful corrective or adaptive action, repairing when possible, and predicting silicon failures early. The whole process is driven by in-chip SLM IP, and only 草榴社区 has the required portfolio and supporting software to provide a complete solution. Visit the 草榴社区 Silicon Lifecycle Management web page for more information.