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Opportunities and Threats

While the growth of the market is good news for mobile manufacturers, the relentless spread of applications is both an opportunity and a threat. In essence, the more tasks that people can complete on a mobile device, the more time that they spend on the device and the more frustrated they become when the battery runs out. The problem is exacerbated because some of the latest apps, like those for fitness, are "always on" and commonly communicate with sensors, creating an even bigger power drain.

There are a few "alternative solutions" to counter the problem of running out of charge. For example, some people carry back-up batteries or cases with built-in batteries. Forward-looking retailers offer in-store charging facilities so that their customers can continue to enjoy the "multi-channel" experience ¨C shopping online, sending them offers ¨C while browsing in-store.

Manufacturers could fit higher-capacity batteries, but that would mean bigger, heavier, hotter products, all of which are likely to turn consumers off. Until battery technology takes a quantum leap forward, chip design teams must use every available technology and design advantage to minimize power consumption while maintaining performance to keep consumers happy.

DRAM Power Drain

After the display screen and application processor, DRAM memory is one of the biggest consumers of power within mobile devices. What's more, DRAM memory bandwidth increases in line with screen resolution and processor performance, which leads to even more power drain. 4K video (3840 x 2160), which was originally conceived for home entertainment and large TV screens, has already found a place on the spec sheets of recent laptops, but the prospect of 4K used for tablet devices is a true innovation.

The trend toward bigger, higher-resolution screens in mobile devices exacerbates the power problem along with the general move towards higher performance systems, and memory bandwidth is at the heart of many of these performance enhancements.

LPDDR3 is the DRAM of choice for many of the latest smartphones, given that it supports bandwidth of up to 2133 Mbps and incorporates a number of power-saving features, including low standby and signaling power and 1.2 V operation. LPDDR3 won't support the bandwidth and low-power needs of the forthcoming generation of devices, which is why the industry is hungry for the next generation: LPDDR4. LPDDR4 SDRAM, designed specifically for mobile applications, will actually be faster than the memory parts that go into today's PCs and servers.

Coping with More Power Demands

LPDDR4 promises more bandwidth: initially 3200 Mbps with the potential to increase to 4266 Mbps with future frequency extensions. The JEDEC standard in development is capable of supporting higher data rates by using a flexible two-channel per die architecture and low-voltage signaling technology. Low-power enhancements and a narrower address bus will reduce the energy required per bit, but transferring more bits means that the overall power consumption may be higher than an LPDDR3 implementation at the highest speeds of operation. Because LPDDR4 will find a place in the highest performance, most complex systems, power management becomes even more critical.

To avoid thermal issues, system designers can use strategies such as monitoring the SDRAM's internal die temperature, increasing the refresh rate, and throttling back the SDRAM clock when it is detected that the die is about to overheat. This may only be necessary when the device is used during extremely compute intensive tasks such as real time gaming, which draws more power and increases the heat dissipated.

DesignWare LPDDR4 IP Features

²ÝÁñÉçÇø offers a complete DesignWare? LPDDR4 IP solution, which includes the LPDDR4 multiPHY with I/Os, the Enhanced Universal DDR Memory Controller and verification IP, as well as hardening and signal integrity services to ease integration and accelerate time-to-market. It supports up to 3200 Mbps with low power consumption, which enables design teams to exploit the full bandwidth of the LPDDR4 standard to maximize system performance. The IP solution also supports switching between separately trained frequencies to tailor performance to meet the needs of the application while still minimizing power consumption.

The IP is backward compatible with LPDDR3 and DDR3/4 SDRAMs, which simplifies design transition from one SDRAM standard to the next. It supports all key LPDDR4 features, with multiple power-saving modes (including power-down, self-refresh and deep power-down), as well as clock gating and selective power down of parts of the PHY that are not in use. 

The DesignWare LPDDR4 IP supports a split PHY implementation to permit designers to distribute the IP around the SoC, optimizing the interface for area-efficient package-on-package (PoP) assembly and offering a low-risk evolutionary path from previous-generation mobile memories. Designers can take advantage of ²ÝÁñÉçÇø' DDR hardening and signal integrity services to harden the LPDDR4 multiPHY and to analyze the signal integrity of the entire system (PHY, SoC, package and system), easing IP integration and reducing potential risks. Support for PoP reduces PCB area in smartphones, while memory-on-PCB support allows for bandwidth and capacity expansion for tablets, notebooks and ultraportable laptops.

Support for PoP reduces PCB area in smartphones, while memory-on-PCB support allows for bandwidth and capacity expansion for tablets, notebooks and ultraportable laptops.

Summary

LPDDR4 memory will be used in mobile devices to enable powerful computing, high-resolution video, larger displays with more pixels, and an enhanced user experience, all while maintaining battery life. LPDDR4 is expected to rapidly become mainstream technology for mobile platforms.

²ÝÁñÉçÇø has established itself as the leading provider of DDR IP with more than 800 design wins over a 15-year period. The company has used its extensive experience to develop a high-performance and high-quality, complete LPDDR4 IP product portfolio consisting of LPDDR4 PHYs, LPDDR4 controller, verification IP, signal integrity and hardening services.

The ²ÝÁñÉçÇø Enhanced Universal DDR Memory Controller IP with support for LPDDR4 is available now. The DesignWare LPDDR4 multiPHY IP is scheduled to be available later in 2014 in a leading 16-nm FinFET process technology. Verification IP for LPDDR4 is scheduled for early availability later this year.

For more information about ²ÝÁñÉçÇø DDR Memory Interface IP solutions including LPDDR4, please visit http://www.synopsys.com/ddr.