²ÝÁñÉçÇø

High test coverage solution for the UCIe interface is achieved by implementing extensive testability features in the UCIe IP to route-out defective dies at the naked die testing phase. Some of the features include:

1-      Scan chains covering all synthetized digital circuitry

2-      Dedicated block specific BIST functionality

3-      Loopback built-in self-test (BIST) functionality covering the complete signal chain up to the IO pin

4-      Programmable pseudorandom binary sequence (PRBS) and user defined test patterns generators and checkers

5-      Error injection to eliminate false passes

In addition, functionality to extend coverage to the die-to-die link, after package assembly can help achieve a high level of test coverage, including:

6-      Far side (die-to-die) BIST loopback functionality

7-      Die-to-die link BIST

8-      2D eye margining to analyze marginalities

9-      Per lane test and repair functionality

Advanced packages enable high density routing with fine pitch micro-bumping and routing on silicon or RDL interposers. During the assembly process, some micro-bump connections may not be well formed and may break down. UCIe offers the ability to test and repair these connections after assembly in a way that recovers the potential yield loss.

UCIe test and repair is executed during production test and at link initialization. In the test phase each individual link is checked for defects at slow speed. Defective links are repaired by re-routing data to spare links that are pre-defined by the UCIe standard.

UCIe configurations targeting advanced packages include up to 8 spare pins per direction (TX and RX) to enable repair of all the functional links:

1- Four spare pins for data pin repair, 2 pins for each group of 32 data pins

2- One spare pin for clock and clocks and track pin repair

3- Three spare pin, each for valid pin, sideband data pin and clock data pin repair

The test and repair execution occurs when there is no valid traffic on the die-to-die link. After repair is complete and the link is initialized, it is assumed to be good and that traffic can be passed without problems. The resulting PHY configuration, called the PHY repair signature, is stored in internal registers in both ends of the link.

Degradation, due to aging or other, of a microbump characteristics during operation may impact link performance. This will be detected at the protocol level by an increase in bit-error rate (BER) or, worst, by data being lost. In that case, the link is expected to be interrupted and a new test and repair step carried out.

However, some applications have stringent requirements in terms of continuity of traffic on the die-to-die link ¨C they cannot tolerate interruption of traffic during operation. For these cases, a testability solution adds Signal Integrity Monitors (SIM) to each UCIe receiver pin.

SIM monitors are small blocks embedded on the receiver. They are constantly sensing the signal at the receiver pin, during normal operation, to identify variations in the signal characteristics which can impact the link performance or indicate that the link is no longer healthy and may break in the near future.

The data gathered by the individual sensors is collected in a Monitoring, Test and Repair (MTR) controller, outside of the interface, for further processing. Aggregating the data from multiple UCIe links can provide instant insights into the health of the multi-die system and enable predictive maintenance of links.

If a specific link is predicted to be at risk of malfunction through this procedure, it can be disabled and data re-routed to one of the spare links, leveraging the UCIe PHY repair mechanism, even without traffic interruption.