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²ÝÁñÉçÇø¡¯ Multipronged Compliance Approach

Compliance is an objective from day one of IP development, and a network of measures and interworking mechanisms have been set in place with this objective in mind. Although the ²ÝÁñÉçÇø methodology minimizes roadblocks and accelerates processes, it is ²ÝÁñÉçÇø¡¯ array of industry-tested tools and prototyping environments, along with its experienced team, that results in IP validation, verification, and compliance (Figure 1). 

Controller Development for Certification Success

The preparation for compliance testing applies to every phase of the controller development, helping to drive the schedule and collaboration process with the engineering teams involved in deliverables such as the PHY, simulation verification IP (VIP) models and software drivers. The process insures continuous feedback and systematically adds redundant checks. Team efforts are not limited to interaction between ²ÝÁñÉçÇø engineers, as considerable effort is allocated to participating and contributing to the specification process itself. In-depth participation in the specification process helps to ensure that the engineering teams thoroughly understand the requirements of the tools, test equipment, and associated test specifications. This includes collaboration with the USB Peripheral Interoperability Lab (PIL), used for early compliance testing until certified test-houses are ready.

²ÝÁñÉçÇø' compliance focus serves to drive several aspects at the architecture phase, where configurability and programmability play a key factor in responding to the possible changes to test specification and interoperability issues with devices/host that may or may not have reached specification maturity. The compliance-driven design approach can even be observed within the implementation stage, where ASIC design engineers are well aware of the associated compliance test applicable to his/her block, as well as the inter-dependencies that exist between them.

The verification phase of a complex protocol such as USB 3.1 Gen 2 represents a paramount effort where constrained random regression approaches can take considerable time to go through thousands upon thousands of coverage points. Parallel efforts focused on direct test scenarios that address compliance test simulation environments are actively sought after to improve the process. For example, the link layer compliance test is a perfect candidate for writing direct test cases. Each test case is generally short and tests a specific reference in chapter 7 of the USB 3.1 specification. The test descriptions provide details to the packet level and define clear assertions for passing or failing criteria. Those direct tests help us run compliance tests early and continuously throughout the design cycle.

PHY IP for Silicon Success

²ÝÁñÉçÇø PHY IP is designed to be robust and to meet the requirements of the USB 3.1 Gen 2 specification, while providing the power and area benefits expected from the industry leader.

The PHY testchip silicon is exhaustively verified within ²ÝÁñÉçÇø laboratories, thanks to the PHY architecture which allows for the transmitter (TX) and receiver (RX) of the PHY to be operated standalone, with pattern generators and pattern matchers incorporated into the PHY itself. When combined with the PHY prototyping board, the PHY can transition through power states as well as transmit and receive a wide range of standardized test patterns. This allows for verification of the electrical performance of the PHY across process, voltage and temperature. Figure 2 shows compliance testing in the lab, where we subject the PHYs to temperatures ranging from -40C to +125C and with varying voltages.

Prototyping ¨C A Critical Key to Success

Preparing the PHY for certification starts long before silicon arrives in the lab. As process nodes become smaller and transistor models more complex, there is a direct impact on the complexity and processing time for simulation. Fast time to tape out is achieved by leveraging ²ÝÁñÉçÇø tools and expertise in this area. The same hardware used for PHY validation is also used for prototyping, both to support compliance testing and to allow customer evaluation of the IP, resulting in our IP Prototyping Kits. The prototyping platform is critical to demonstrating full USB functionality.

The hardened portion of the PHY IP is incorporated into a testchip wrapper and implemented in silicon. The USB 3.1 PHY IP prototyping board supports the test chip silicon for the PHY as well as FPGAs that implement the PHY Physical Coding Sublayer (PCS). When connected to a ²ÝÁñÉçÇø HAPS FPGA-based development system that integrates the ²ÝÁñÉçÇø USB 3.1 PHY IP, the result is a complete IP Prototyping Kit. This IP Prototyping Kit shown in Figure 3, behaves like a thumb drive during testing, allowing for files to be transferred across the USB 3.1 interface and stored.

The USB 3.1 Gen 2 specification requires high clock frequency for certain logic regions of the controller. Using the prototyping system, ²ÝÁñÉçÇø engineers applied their knowledge of the protocol and the clock frequency requirement to design a configurable datapath that can be synthesized for either ASIC and FPGA modes.

As USB PHY speeds increase, the physical requirements of IP prototyping boards become more demanding. For instance, the move from USB 3.0 to USB 3.1 Gen2 requires an order of magnitude change in the complexity of the transmission line design. ²ÝÁñÉçÇø has considerable expertise in the area of high-speed PHY board design, which our customers benefit from in the form of reference designs and support. In addition, the ²ÝÁñÉçÇø controller provides powerful debug methods to accurately locate root cause of failures, such as different levels loopback mode. Together with ²ÝÁñÉçÇø RTL instrumentor and Deep Trace Debug, the controllers greatly accelerate the prototyping process.

Combined with the full IP Prototyping Kit, pre-compliance testing can begin. The compliance tests evaluate TX signal quality, adaptive RX equalization and RX jitter tolerance. For the PHY, the most complex of these tests is the jitter tolerance testing of the receiver. Jitter Tolerance Testing (JTOL) requires careful calibration, and during the early years of compliance certification, the calibration procedure for JTOL can change from week to week. Having detailed knowledge of the JTOL calibration procedure allows ²ÝÁñÉçÇø engineers to ensure that our IP will pass with margin to spare, as well as to quickly diagnose test setup and calibration issues at the test house.

Bring it all together

In the early stages of its implementation, a protocol like USB 3.1 Gen2 is constantly evolving. The specification, test requirements, and design required all change dynamically. To succeed in attaining certification in this kind of environment, every resource, from hardware and software engineering, to system architects and protocol specialists, must be leveraged for efficiency and quality. Companies must respond with agility and speed when confronted with specification and design iterations, hardware issues, and other challenges arising from the integration of multiple blocks of IP. ²ÝÁñÉçÇø has proven its methodology by being the first IP company to achieve certification for USB 3.1 Gen2, in the most challenging USB certification environment in the history of the standard.