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Introduction

As applications such as near-field communications (NFC), radio-frequency identification (RFID), and advanced sensors require more embedded non-volatile memory (NVM), designers are driven to incorporate advanced NVM technology to meet system demands. This article will highlight the key power, area, and reliability requirements of these markets and show how the requirements continue to change over time. It will also cover how ²ÝÁñÉçÇø has leveraged patented device and design-level innovations to reduce NVM IP area and power by over 50% over previous generations, and the impact of these innovations on system-level design and performance.

Importance of Endurance in Sensor Systems

Real-time data logging is now more prevalent than ever. From measuring your blood pressure to real-time stress on a steel bridge, sensor networks are quickly driving a new age of data collection, aggregation and analysis, all requiring higher endurance in multiple-time programmable (MTP) NVM.

As shown in Figure 1, sensor system¡¯s requirements depend on how much EEPROM is needed and how often the data needs to be written. The answers not only affect area and power (e.g., a large EEPROM generally takes more power) but also drive the endurance and retention requirements.

To minimize the endurance challenges, designers must use IP that starts with the fundamentals and then innovates with custom devices, leading edge tools and state-of-the-art design. Understanding MTP NVM requires an expertise in how charge is transferred during program and erase cycles. This expertise is used to optimize performance over different manufacturing materials and layout through monitoring voltage, current and manufacturing level stressors during the development process, as shown in Figure 2.

Reducing Power Consumption and Area Use

When most people think about power, they focus on battery life, but power decisions also affect area and dynamic performance. Lowering power consumption increases system performance by allowing battery or RF-powered MTP NVM devices to function for a longer time and from further away or through using smaller antennas. Reducing power can also lower system area, enabling lower cost and a wider range of packaging options. There is often a link between power and area and this combined reduction enables new applications such as RFID and Internet-of-Things (IoT).

When power is a key concern, starting with a technology evaluation can be the right approach followed by balancing how much NVM is needed in the system. As an example, higher density memories will typically require higher peak and average currents while NVM programming mechanisms (e-injection, blown gate, FN tunneling, etc) differ in currents as well. Figure 3 illustrates some fundamental differences between two popular programming mechanisms that can have an effect on supporting circuits and total area of the NVM.

In addition, there are also system-level concerns where the choice of NVM technology and density may negatively impact other components. Applications that deal with high impedance supplies must take care that peak currents don¡¯t dynamically push their system VDD outside the operating range of other on-chip components. At the system level, physically larger voltage regulators and batteries can be used to counteract high currents, but may have a negative impact on product size, cost and performance.

For low-power/low-cost applications, making the right NVM choice is critical. Designers should ask themselves:

1. What do I need to understand about the NVM technology?

• Is low power a key differentiator?
• Is the technology mature and manufacturable?

2. How does NVM performance affect other components in your system?

• Does it cause other components to grow or shrink in area and power?

3. What is the system level impact (area and power) of higher or lower density NVM solutions?

• Can I use a small amount of MTP/NVM + ROM?
• Do I need a large amount of MTP/NVM?

Trusting Your NMV IP Solution

From storing passwords to GPS settings, end users typically don¡¯t think about NVM¡ªthey blindly trust it.

This trust didn¡¯t happen by accident. It was built through product developers carefully evaluating application needs. These needs were then combined with the track record and evolution of NVM suppliers. When incorporating NVM IP, designers should understand their expectations for:

• Data retention and endurance cycles
• Manufacturability and yield
• Performance, both now and in the future

Studying standard specs and data can be a straightforward comparison between NVM technologies, but designers must also consider additional factors when selecting an NVM IP supplier:

• Supplier¡¯s history of growth and adaptation to changing markets
• Supported manufacturing options
• Supported quality levels (e.g. commercial, industrial, and automotive)
• Data retention¡ªwill the supplier still be around in 10 or more years?

²ÝÁñÉçÇø Innovation with DesignWare MTP NVM IP

²ÝÁñÉçÇø¡¯ 180 nm MTP NVM technology was first productized in 2003. Since then, ²ÝÁñÉçÇø NVM IP has shipped in over 3 billion units. As part of its drive for technology leadership, ²ÝÁñÉçÇø is focused on area reduction, which results in cost savings for designers. Figure 5 highlights ²ÝÁñÉçÇø¡¯ track record of continued area reduction in the 180 nm node for 1kbit MTP NVM. 

This area reduction has also been combined with reduced metallization and power reduction, as shown in Figure 6. ²ÝÁñÉçÇø closely collaborated with its customers to develop MTP NVM IP that meets their area, power, and performance requirements.

1. Smaller area ¡ú Lower capacitance/ Lower power

• Innovative bitcell and HV architecture minimize area and capacitive loading

2. Slew rate control ¡ú Reduced peaks

• Optimized internal drivers are tuned to reduce peak and average power

3. Increased efficiency ¡ú Doing more with less

• Innovative HV circuits reduce both loading and analog/digital complexity

View more information about ²ÝÁñÉçÇø¡¯ DesignWare MTP NVM IP solution.