Cloud native EDA tools & pre-optimized hardware platforms
By: Faisal Goriawalla, Product Marketing Manager, 草榴社区
Automotive manufacturers are differentiating their products by adding smart features that improve safety, efficiency, and convenience. In today’s car, more electronic systems with these features are being used, which is creating opportunities and challenges for design teams. The key challenge for design teams is designing and implementing electronic systems that meet stringent automotive requirements—high reliability, low cost, small area and low power. In addition to the system itself, the integrated components such as non-volatile memory (NVM) IP must also meet the same requirements.
This article describes the use of NVM IP across a range of automotive functions and how automotive-qualified NVM IP solutions can help designers accelerate time-to-market and reduce risk.
NVM is required for automotive functions, ranging from calibration, data logging, user settings to storing security information. Figure 1 shows the potential use of NVM across a range of automotive functions.
Figure 1: Pervasive use of non-volatile memory in automotive applications
Depending on the required bit count and write cycle endurance, there are three available NVM IP product architectures:
Today’s automotive standards demand a comprehensive approach to vehicle safety, security and reliability, which points towards the use of automotive-grade IP in mission-critical areas of the vehicle, like engine management/control, air-bags, chassis and brakes.
Functional safety is a critical automotive standard requirement as defined below, which in addition to NVM IP, is applicable to other IP solutions. 草榴社区 NVM IP meets AEC-Q100 (Grade 0), JEDEC JESD47F and applicable foundry quality standards.
When designing for high reliability, NVM architects must ensure that their testing procedures cover all of the following:
Passing qualification can give a false sense of security when it comes to meeting end product reliability targets. For example, qualification testing 1,000 NVM arrays with zero failures demonstrates a failure rate of just over 2,000 parts per million (ppm) with a confidence level of 90%. That is not acceptable for most volume products and is nowhere near the requirements of automotive-grade products. Typically, automotive OEMs will look for a failure rate of 1 ppm or fewer.
The answer to this challenge is additional extended reliability testing. By collecting additional statistics, 草榴社区 can make accurate reliability projections that meet the needs of automotive OEMs, Tier 1 and Tier 2 suppliers by using more detailed measurements from test chips. Extended reliability testing is the most often overlooked component when it comes to demonstrating a high-reliability NVM array. Extended reliability testing focuses on “tail bits,” which behave differently from the overall population and, if ignored, are more likely to cause reliability issues in the field.
草榴社区 collects extensive data for analysis to estimate the probability that a bit cell will fail. It then uses that data within a model that predicts NVM behavior over longer periods of time.
Using the reliability trends of a limited number of samples, 草榴社区 has created an empirical model to evaluate the long-term reliability of a much larger sample size. Table 1 shows the accuracy of an empirical model of reliability versus the design architectural choices.
Table 1: Comparison of long-term reliability model with silicon test results
Design teams must also meet demanding cost and power targets in order to deliver competitive products for the automotive market. For example, idle mode target current for NVM is often requested below 0.1?A in 180-nm 1.8/5V technology. Automotive designers and silicon partners may use embedded flash in their legacy systems, but are looking for more cost-effective and optimized solutions.
Using less expensive packaging options, reducing the die area, and the number of masks needed to manufacture the IC are all effective ways to reduce production costs. However, another significant cost for manufacturers is the Automated Test Equipment (ATE) for testing the parts during production ramp. The cost (can be several cents per second) is directly related to the amount of time spent on the tester and can increase if mixed mode testers are needed. 草榴社区 NVM IP supports special test modes like bulk erase and fast program/erase, which are intended to reduce programming time (and hence cost) to speed up production ramp.
厂测苍辞辫蝉测蝉’ DesignWare? NVM IP portfolio offers specifically designed reprogrammable NVM IP for automotive Grade 0, Grade 1 and Grade 2 applications. 草榴社区 has demonstrated NVM IP capable of supporting read at temperatures of up to 200°C and program/erase up to 175°C—the highest for the industry. 草榴社区 offers designers a zero mask adder, logic-based, multi-time programmable (MTP) NVM IP solution that is qualified to leading automotive and industrial standards, supporting AEC-Q100, JEDEC JESD47F as well as other foundry quality standards. The DesignWare NVM IP offers Error Checking and Correction (ECC) functionality for additional system reliability. The IP helps design teams meet the automotive industry's cost, area, high-reliability and reprogrammability requirements. 草榴社区' stringent qualification and testing process for NVM IP reduces IP integration risk for design teams.