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NVM in Automotive

NVM is required for automotive functions, ranging from calibration, data logging, user settings to storing security information. Figure 1 shows the potential use of NVM across a range of automotive functions. 

Depending on the required bit count and write cycle endurance, there are three available NVM IP product architectures:

• Reprogrammable Electrically Erasable Programmable Read-Only Memory (EEPROM) is needed for high-endurance applications.
• Few-Time Programmable (FTP) TRIM is suited to coefficient/parameter storage for sensors and analog integrated circuits (ICs) needing up to 1K (worst case) endurance cycles.
• Higher bit-count medium density architecture is needed as a low-cost embedded flash (e-flash) replacement, especially to bipolar CMOS DMOS processes.

Today¡¯s automotive standards demand a comprehensive approach to vehicle safety, security and reliability, which points towards the use of automotive-grade IP in mission-critical areas of the vehicle, like engine management/control, air-bags, chassis and brakes.

Ensuring Functional Safety

Functional safety is a critical automotive standard requirement as defined below, which in addition to NVM IP, is applicable to other IP solutions. ²ÝÁñÉçÇø NVM IP meets AEC-Q100 (Grade 0), JEDEC JESD47F and applicable foundry quality standards.

• The AEC-Q100 standard: Determines that a device is capable of passing specified stress tests and thus can be expected to give a certain level of quality/reliability in the application. To meet the AEC-Q100 standard, automotive design teams have to design to a certain temperature grade to adhere to the functional safety needs of the specific application. Grade 0 is the most stringent standard and specifies an ambient temperature range from -40?C to +150?C.
• Foundry standards: Some foundries have their own internal acceptance standard, which specifies a strict set of requirements for validation and qualification of parts based on statistical analysis of a minimum number of samples across multiple process splits.
• The JEDEC JESD47F standard: Specific to automotive ICs and IP and relates to the stress-test-driven qualification of ICs.

High Reliability Targeting <1 DPPM (Defective Parts Per Million)

When designing for high reliability, NVM architects must ensure that their testing procedures cover all of the following:

• Characterization: Ensure that the NVM IP is manufacturable in high volumes.
• Qualification: Ensure that the NVM IP meets all appropriate industry standards.
• Reliability: Ensure that the NVM IP meets the target reliability specifications.

Passing qualification can give a false sense of security when it comes to meeting end product reliability targets. For example, qualification testing 1,000 NVM arrays with zero failures demonstrates a failure rate of just over 2,000 parts per million (ppm) with a confidence level of 90%. That is not acceptable for most volume products and is nowhere near the requirements of automotive-grade products. Typically, automotive OEMs will look for a failure rate of 1 ppm or fewer.

The answer to this challenge is additional extended reliability testing. By collecting additional statistics, ²ÝÁñÉçÇø can make accurate reliability projections that meet the needs of automotive OEMs, Tier 1 and Tier 2 suppliers by using more detailed measurements from test chips. Extended reliability testing is the most often overlooked component when it comes to demonstrating a high-reliability NVM array. Extended reliability testing focuses on ¡°tail bits,¡± which behave differently from the overall population and, if ignored, are more likely to cause reliability issues in the field.

²ÝÁñÉçÇø collects extensive data for analysis to estimate the probability that a bit cell will fail. It then uses that data within a model that predicts NVM behavior over longer periods of time.

Using the reliability trends of a limited number of samples, ²ÝÁñÉçÇø has created an empirical model to evaluate the long-term reliability of a much larger sample size. Table 1 shows the accuracy of an empirical model of reliability versus the design architectural choices.

Power Consumption and Driving Cost Down

Design teams must also meet demanding cost and power targets in order to deliver competitive products for the automotive market. For example, idle mode target current for NVM is often requested below 0.1?A in 180-nm 1.8/5V technology. Automotive designers and silicon partners may use embedded flash in their legacy systems, but are looking for more cost-effective and optimized solutions.

Using less expensive packaging options, reducing the die area, and the number of masks needed to manufacture the IC are all effective ways to reduce production costs. However, another significant cost for manufacturers is the Automated Test Equipment (ATE) for testing the parts during production ramp. The cost (can be several cents per second) is directly related to the amount of time spent on the tester and can increase if mixed mode testers are needed. ²ÝÁñÉçÇø NVM IP supports special test modes like bulk erase and fast program/erase, which are intended to reduce programming time (and hence cost) to speed up production ramp.

DesignWare NVM IP

³§²â²Ô´Ç±è²õ²â²õ¡¯ DesignWare? NVM IP portfolio offers specifically designed reprogrammable NVM IP for automotive Grade 0, Grade 1 and Grade 2 applications. ²ÝÁñÉçÇø has demonstrated NVM IP capable of supporting read at temperatures of up to 200¡ãC and program/erase up to 175¡ãC¡ªthe highest for the industry. ²ÝÁñÉçÇø offers designers a zero mask adder, logic-based, multi-time programmable (MTP) NVM IP solution that is qualified to leading automotive and industrial standards, supporting AEC-Q100, JEDEC JESD47F as well as other foundry quality standards. The DesignWare NVM IP offers Error Checking and Correction (ECC) functionality for additional system reliability. The IP helps design teams meet the automotive industry's cost, area, high-reliability and reprogrammability requirements. ²ÝÁñÉçÇø' stringent qualification and testing process for NVM IP reduces IP integration risk for design teams.