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The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity creates two major challenges: manufacturability and cost. From a manufacturing perspective, these processing engines are approaching the maximum size of the reticle that the lithography machine can etch; and with a very large die size and correspondingly decreasing yield, the cost per die can increase significantly.

Gordon Moore once said, “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.” In chip design, to address the demands of increased performance, the industry is moving from system-on-chip (SoC) to system-in-package (SiP) by using wafer-level packaging.

A heterogeneous SoC entails partitioning the SoC at the IO or core level, using a modular approach with different building blocks. This offers several advantages, including supporting SoCs that are growing beyond reticle size, improving die yield, and enabling design modularity. However, a heterogeneous die introduces new challenges which include increased design complexity due to close interaction between the dies and package, supporting testability across assembly and manufacturing processes, and thermal management due to the proximity of the dies. 3D integration enables heterogeneous integration of IC chips fabricated with different technologies and materials, and thus permits the realization of integrated, sophisticated, and multifunctional microsystems that have high performance, low cost, and compact size requirements.

Emerging semiconductor applications that require the processing of massive quantities of data are driving the progress of advanced packaging. Various advanced packaging technologies, side-by-side or vertical placement, have emerged as part of the implementation of heterogeneous integration technology. 2.5D and 3D packaging have gained popularity as prominent solutions, each offering unique advantages and challenges, making them essential considerations for semiconductor manufacturers and designers.

In 2.5D packaging, two or more chips are laid side by side with an interposer connecting one die to another. The interposer acts as a bridge, connecting the individual dies and providing a high-speed communication interface, allowing greater flexibility in combining different functionalities on a single package. By stacking dies on an interposer, 2.5D packaging reduces the overall footprint of the package (compared to 2D), making it ideal for smaller and thinner devices. Interposers and bridges provide a large number of high-density BUMPs and traces, which helps in increasing bandwidth.

In 3D IC technology, chip connections are made through vertical stacking, enhancing the overall performance and functionality of the package. This allows the integration of chiplets with multiple layers and functionalities. A key trend of this integration – especially for 3D packaging technologies such as hybrid bonding – has led to an aggressive shrinking of the BUMP pitches between the chiplets and the resulting reduction of the corresponding interconnect distances and related parasitics.

Driven by the demands for greater bandwidth and advances in manufacturing processes and packaging technologies, there has been a significant change in interconnects from traditional copper uBUMP to the most advanced uBUMP using 40um pitch, scaling even further down to 10um (Figure 2).