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By: John A. Swanson, Product Marketing Manager, ²ÝÁñÉçÇø

According to the  news release, the data center market ¡°is estimated to grow from USD $36.47 billion in 2016 to USD $90.56 billion by 2021, at a high Compound Annual Growth Rate (CAGR) of 19.95% during the forecast period.¡± Such growth is due to the significant rise in the number of connected devices and the need for quick processing of high-volume data. The need for higher performance and the fact that much of the data travels through an Ethernet port drove the development and evolution of the 25G high-speed Ethernet standard and its associated standards. Prior to the introduction of 25G Ethernet, 40G (4 lanes of 10G) was the next speed for data centers and the path to 100G was 10 lanes of 10G. As you can see in Table 1, looking at total bandwidth, the introduction of the 25G lane speed provides a scalable path to 100G while achieving significantly improved bandwidth when compared to 40G Ethernet. 

Table 1: 25G port speed provides a scalable path to 100G with additional lanes per port

The 25G Ethernet was first introduced by the Optical Internetworking Forum (OIF) in 2011. The 25/50G Ethernet Consortium developed specifications for a single 25G lane MAC and PCS and leveraged the Institute of Electrical and Electronics Engineers¡¯ (IEEE) 100G SerDes development for 100G Ethernet. Now, in addition to the initial consortium specification, there is a published set of standards from the IEEE as part of the IEEE 802.3 standard.

This article describes the 25G Ethernet specification as currently defined by the IEEE and associated consortium, and outlines the complete PHY and controller IP solutions that designers need to drive higher performance for high-end data center SoCs. 

25G Ethernet Standards and Target Applications

The 25G/50G Ethernet Consortium, an open organization, initially defined the 25G Ethernet standard and promoted it through its member companies. According to the Consortium¡¯s , ¡°The 25 Gigabit Ethernet Consortium enables industry participants to develop new technologies that function in accordance with the specification(s) outlined in the consortium agreement in order to benefit consumers and the industry by facilitating accelerated adoption of 25G and/or 50G technologies.¡± Based on the Consortium¡¯s initial work, IEEE standards for 25G Ethernet are now defined in both single lane and 4 lanes of 25G. Table 2 shows IEEE standards associated with 25G Ethernet with related electrical specifications. 

Table 2: IEEE defined standards for 25G Ethernet and its target interfaces 

With this set of clearly defined standards within the IEEE, 25G Ethernet and its aggregated forms are the new standards for mainstream connectivity in the data center, enabling more data transition in less time and at reduced cost. The standard supports various hardware interfaces such as chip-to-chip, chip-to-module and backplane. Chip-to-chip and chip-to-module at 25G significantly improve the overall system performance, while backplane Ethernet supports the evolving blade server market specifically moving from 1G to 10G and now 25G. Figure 1 shows how 25G Ethernet can be used to both drive interconnect between the different chips/modules as well as the connection for modules via passive or active cables at the port side. It also shows the 25G Ethernet standards that can be applied for either a single lane 25G Ethernet, a 2x25G for 50G Ethernet or a 4x25G for 100G Ethernet. This flexibility gives designers a powerful set of interfaces that can be used in applications ranging from the switch fabric, traffic managers, and as interconnect to other modules in the server.

Figure 1: Pictorial view of 25G Ethernet applications on a data plane

25G Ethernet IP

To address the challenges of achieving the required system throughput, meeting the timing budget and supporting selected 25G Ethernet features, designers need a flexible solution that includes a complete subsystem including the media access controller (MAC), physical coding sublayer (PCS), and serializer/deserializer (SerDes).

Supporting data rates from 1G to 100G, the DesignWare Enterprise Ethernet MAC IP is designed for three different system level configurations: MAC only, MAC with the memory controller, and a complete direct memory access (DMA) with the ARM? AXI Interface. With a native 128-bit FIFO interface for minimal latency, jumbo frame support and a range of application-specific configurations, designers can easily integrate the application-tailored MAC into their design.

The DMA interface is included to ease the migration of 10G designs to 25G designs as the first generation of mass-deployed 10G designs often use the ARM AMBA on-chip interconnect. To facilitate this migration from 10G to 25G Ethernet, the DesignWare Enterprise MAC¡¯s optional AMBA AXI interface can support 128-bit data transfers with up to 16 transmit and receive channels.

The MAC has a separate DMA channel in the transmit path for each queue in the MAC transaction layer (MTL) - Single or multiple DMA channels for any number of queues in MTL Receive path, and individual programmable burst size for Tx DMA and Rx DMA engines for optimal host bus utilization. Some of the main configurable options in the descriptor include:

• Byte-aligned addressing
• Dual-buffer descriptor ring and support for 64-bit addressing
• Descriptor architecture to allow large blocks of data transfer with minimum CPU intervention
• TCP Segmentation Offload (TSO) and IEEE 1588 Timestamps
• One-step PTP time correction in Tx
• Option to provide 64-bit Timestamp for received packets
• Option to give up to two VLAN tags in descriptor for insertion or replacement in Tx and stripped VLAN tags in Rx
• Option to split the packet header (layer 3 and layer 4) and layer 4 payload in different buffers
• Delivers RSS hash information for packets received with TCP/UDP over IP payload

The DesignWare Enterprise MAC is easily integrated with the ²ÝÁñÉçÇø PCS layer. The PCS is configurable for a range of connectivity and provides support for both IEEE and consortium specifications for 25G Ethernet. Some of the key optional modules include the Read Solomon Forward Error Correction (RS-FEC) block defined by Clause 74 or Clause 91 of the IEEE 802.3 specification, link training support, and auto-negotiation. The PCS supports multiple interfaces including single 25G, 2x25G for 50G Ethernet, and 4x25G for 100G Ethernet. Details on the different configuration options are included in ²ÝÁñÉçÇø coreConsultant.

The Enterprise MAC and PCS integrates seamlessly with the DesignWare Multi-Protocol 25G PHY IP. The PHY delivers outstanding signal integrity and jitter performance for data center applications and is extremely low in area and power with support for Energy Efficient Ethernet (EEE). The configurable transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance, and the continuous calibration and adaptation (CCA) provides robust performance across voltage and frequency variations.

With ²ÝÁñÉçÇø¡¯ multi-protocol 25G PHY, all the components needed for a 25G Ethernet solution are available and fully tested to ensure designers can easily integrate the subsystem solution into their design, or as components of their design. With the PHY, designers can accomplish challenging tasks such as full subsystem simulation, synthesizing the subsystem with several different target libraries, timing closure, and placement and routing. ²ÝÁñÉçÇø provides the implementation and verification scripts for easy subsystem configuration of their target applications.

Conclusion

The 25G Ethernet standard, initiated by the 25G/50G Consortium and now by the IEEE, is expanded to a robust set of published and approved standards as part of IEEE 802.3. It is the new standard for connectivity in the data centers. The specification allows for transmission of more data in less time, and supports multiple hardware interfaces to give designers flexibility in designing their SoCs for various high-end computing applications. With ²ÝÁñÉçÇø¡¯ complete 25G Ethernet solution, designers can overcome the challenges of achieving the required system throughput, meeting timing budgets and supporting the  25G standard.