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Example Models

Designers can choose from an extensive library of example ASIP models provided as nML source code. In combination with ASIP Designer, these models can be used as a starting point for architectural exploration, and customer-specific production designs.

• Trv: Four additional RISC-V ISA models, supporting the F single-precision float instruction class, featuring 32-bit data paths, and both a 3- and 5-stage pipeline
• All Trv models come with optional On-Chip Debugging (OCD) support. The OCD interface uses the automation provided with ASIP Designer, so it is automatically updated for any extensions / modifications made to the Trv models
• ASIP Designer allows the integration of existing RTL components. A new example model illustrates how to integrate a multi-cycle Verilog component. It shows how to use Verilator to build the ISS, making the integration of an existing RTL component into your ASIP simpler than ever
• ASIP Designer supports the integration of the ISS into Virtualizer. A new demo setup illustrating the simultaneous debugging and cross-triggering of a multicore system including a standard processor IP (ARC or Arm) and an ASIP is provided

Processor Modeling

• The nML language has been extended with components, which are parametrized nML blocks that can be instantiated multiple times. nML components allow to efficiently describe parallel instruction slots having a similar structure, as often found in VLIW / ILP architectures
• For the documentation generation from nML, annotations can now directly be added in an attribute annotated to the nML rules. For example, it is less prone to errors in the documentation when the behavior of a rule is changed, since both behavior and documentation are closely together in the same file

C/C++ Compiler

ASIP Designer comes with a unique and patented compiler solution, with the compiler automatically retargeting itself to the processor architecture. This eliminates any need for compiler backend customization by the user. Release 2021.03 offers

• Precise I/O constraint modeling for scheduling, both in terms of dependency lengths, affected instructions, and affected variables.
• Constant pools relative to the global pointer, to load large literals from memory in a position-independent-code (PIC) way
• The LLVM-based front-end, and all example models featuring the LLVM-based frontend have been updated to the most recent LLVM version 12.0. The newlib component in the full library stack has been upgraded to version 4.0

RTL Generation, Verification, and Synthesis Support

• PPA estimation for primitive functions, using an easily customizable nML wrapper that generates a minimal processor context as a light but realistic environment for synthesis. This allows to explore design alternatives for such primitive functions using a quickly generated, real synthesis result, avoiding the need to synthesize the entire processor model for trustworthy results on which implementation decisions can be based
• Simplified integration of a SystemC-wrapped ISS for use in SystemVerilog  test-benches, which  includes the automatic generation of an RCD monitor that compares outputs from RTL and ISS.
• Alternatively, the RTL can be instrumented to generate traces, even during emulation, that allow to replay its behavior with an ISS, comparing outputs ¡°off-line¡±
• Generation of a scripting environment to perform design exploration with ²ÝÁñÉçÇø RTL Architect, enabling an efficient analysis of the generated RTL code