Reducing Glitch Power Waste in Advanced SoCs with a New Methodology

Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this whitepaper, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final signoff.

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