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SoC performance is a key competitive advantage in the marketplace, and the choice and configuration of protocol IP and interconnects is geared towards maximizing said performance. A case in point is the use of HBM (High Bandwidth Memory) technology and memory controllers. Currently in its third generation, HBM boasts of high-performance while using lesser power in a substantially smaller form factor than DDR. That said, how do teams ensure that the performance is delivered in the context of their SoC design?

Thanks to protocol performance analysis and debug tools like Verdi Performance Analyzer, users can easily visualize important performance metrics such as page-hit read latency, etc. (see figure below). Additionally, they can set min. and max. constraints on each metric and have the tool automatically identify violations of these constraints (in yellow and purple). Through direct integration with Verdi Protocol Analyzer, they can then root cause to the offending transactions in a matter of seconds.

While this is very powerful and enormously useful for debug, it¡¯s just the tip of the iceberg. Teams could use a lot more automation in their SoC verification environment, especially for SoC performance verification which oftentimes gets compressed or even neglected due to project deadlines. ²ÝÁñÉçÇø SoC Verification Automation solutions are built exactly for this purpose ¨C VC AutoTestbench for automated generation of testbenches, VC VIP AutoPerformance for automated performance stimulus generation, and Verdi Performance Analyzer for automated protocol performance analysis and debug.

 for the SoC Performance Verification webinar on February 21st to learn more.