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With challenging size, weight, and power (SWaP) requirements, chip designs for aerospace, defense, and government applications are a unique breed. No surprise here, considering systems like satellites and submarines must operate reliably in the distinctly harsh environments of outer space and ocean depths, respectively.

Given the SWaP criteria along with high computation density and diverse applications, monolithic SoCs are proving inadequate for the needs of next-generation systems. Instead, many designers in this realm are, like their commercial counterparts, exploring 3DHI designs. In a 3DHI chip design, heterogeneous dies are integrated into multiple tiers, with vertical die-on-die and horizontal die-to-die interconnections.

A 3DHI architecture enables designers to shrink big systems into small packages and to reduce the cost of variants to meet the application diversity requirements. This, in turn, leads to more application-targeted solutions and better functional density capabilities in addition to superior SWaP outcomes. In this blog post, we’ll take a closer look at the challenges and opportunities of 3DHI for aerospace, defense, and government applications, how the U.S. government is supporting advancements in these technologies, and what’s needed to foster 3DHI success. 

Delivering Bandwidth and Performance, from Drones to Planes

Similar to many other sectors, today’s aerospace, defense, and government systems are marked by greater intelligence, often with automation and cognitive processing that require high computation density. For example, in drones that perform surveillance, the processing must happen in a small form factor with limited power and weight. As experienced by other high-performance computing designs, monolithic SoCs supporting these applications are hitting density, scalability, and yield limits as Moore’s law scaling slows.

3DHI designs provide the advantage of mixing and matching dies from different process nodes and materials, tailored to the functions at hand to deliver the desired functional density and performance. Not every component needs to be at an advanced node, saving related costs, and specialized processes, with materials such as gallium nitride (GaN) or silicon carbide (SiC), can be included with silicon CMOS. What’s more, adopting 3D packaging provides form factor advantages without a bandwidth penalty. The ultra-short latency and power-efficient bit transfers of 3D packages provide a benefit over their 2D counterparts, while being able to use smaller chips can lead to better yields. In addition, a 3DHI approach supports efficient reuse for different applications or design variations, enabling teams to take, say, a design for a manned aircraft and adapt it for a drone.

There is still a ways to go before 3DHI designs can be considered mainstream for aerospace, defense, and government applications. Let’s take a closer look at where we are now, and what’s needed to reach a level of volume production in this sector.

Opportunities for More Chip Design R&D

2D, silicon-based designs with monolithic integration are common in today’s aerospace, defense, and government applications landscape. Some designers in this space are also developing 2.5D and 3D designs, but for specialized purposes, with only a few layers, and at relatively low production volumes. In the next decade or two, 3D designs will likely become the norm in this sector, growing more complex and consisting of many more layers. As we look toward this future, we can anticipate disaggregated designs consisting of bare dies from multiple processes and multiple material types, all connected by dense interconnects. Packaging, along with assembly and test, will be considered in light of how the system will communicate and integrate with the outside world.

From an electronic design automation (EDA) standpoint, a new approach will be required to ensure that higher volume 3DHI designs can function reliably and successfully in aerospace, defense, and government systems. Such designs raise many new questions around considerations such as cross-coupling effects between die tiers and how to connect them; developing trustworthy assemblies; connecting wafers of disparate process nodes, types and even sizes; cooling disparate materials; and so on. It may be prudent to integrate a die test and error correction capability into 3DHI components to proactively address any issues before a system ships and adapt to issues that develop later. Also important are redundancy and resiliency. Due to aging effects typical of any type of silicon device, some of the dies in the system may wear out over time. Developing a design that’s able to adapt should an individual region fail could be one way to protect against an overall system failure.

While the tool flows to address these questions and concerns are still maturing, they do present an upgrade from manual package development. In addition, there are opportunities for research in various areas: multi-die; multi-technology integration and assembly; tools for architecture, design, simulation, and test; security; and thermal and power management, to name a few. The good news is, these considerations involve physics and, ultimately, can be modeled, often with modern digital twin technology. Now is the time to continue to explore and develop tools that enable enough abstraction of the various layers so that design teams can make informed decisions.

Creating an Open-Access Center for 3DHI R&D

Recognizing the need for greater advancements into what it is calling “the next major wave in the manufacture of high-performance microelectronics,” the U.S. Defense Advanced Research Projects Agency (DARPA) has launched its to create a U.S.-based, open-access center for R&D and manufacturing of 3DHI microsystems. NGMM is a key element of ERI 2.0, a DARPA initiative aimed at ensuring domestic leadership in cross-functional, future-focused microelectronics R&D and manufacturing.

As DARPA fosters creation of the 3DHI center, it’s clear that the collaboration of sectors including government, industry, and academia will be critical in getting the effort off the ground. Government provides direction and reduces risk with research funding, businesses tune their technologies and expertise, and academia can focus on groundbreaking research. 草榴社区, for example, has a long history of collaborating with the U.S. government and defense industry leaders. As an Accredited Supplier by the Defense Microelectronics Activity (DMEA) Trusted Foundry Program, 草榴社区 has worked closely with a number of government entities, including DARPA and the Intelligence Advanced Research Projects Activity (IARPA). In the area of 3DHI, we have tools to automate the architecture, design, and verification for multi-die systems, including heterogenous 3DICs, and these flows can run on the cloud for greater scalability and flexibility.

Summary

From radar equipment to aircraft, submarines, and spacecraft, systems for aerospace, government, and defense applications are becoming increasingly intelligent. To meet demands for greater computational capacity and reduced SWaP, design teams must innovate beyond traditional monolithic SoCs. This is why 3DHI designs have emerged in a range of applications, including radar. By bringing together heterogenous dies in a single package, 3DHI designs can deliver the high bandwidth and small form factor that these types of applications require to succeed. There’s plenty of opportunity to tune tool flows and methodologies to address all the key design challenges posed by this type of architecture. Through continued R&D efforts from government, industry, and academia, more robust tools and technologies are poised to emerge and 3DHI designs could become commonplace in this sector over the next decade or so.

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